QLC Flash Memory Controller for Adaptive MSB/LSB Decoding
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Solution Overview
Problem
Existing flash memory devices, particularly those with quadruple level cell (QLC) technology, face inefficiencies in access control due to high bit error rates and instability, which traditional sensing schemes fail to adequately address, especially in high-density storage arrangements.
Innovation Solution
A flash memory controller architecture that includes a microprocessor, control logic, and memory, capable of decoding data by receiving specific bits from memory cells, determining the state of memory cells, and using these bits to efficiently manage access, even in high-density storage, by employing a read mechanism that generates both most significant bits (MSBs) and least significant bits (LSBs) in a single read command, allowing for balanced state detection and efficient decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional sensing schemes are used for reading data from QLC flash memories, then the memory device can operate with high storage density, but the bit error rate increases and decoding accuracy deteriorates
Solution Approach 1:
The patent segments the reading process into multiple phases: first reading MSBs to determine memory cell states, then conditionally reading LSBs only for cells that require additional verification. This segmentation allows efficient handling of high-density QLC memory while maintaining decoding accuracy by applying different reading strategies to different subsets of memory cells based on their state characteristics
Solution Approach 2:
The patent changes the reading parameters dynamically based on the detected memory cell states. After reading MSBs, the system identifies cells with uncertain states and adjusts subsequent reading parameters (voltage levels, timing) when reading LSBs for those specific cells. This parameter adaptation enables accurate decoding in high-density QLC memory where traditional fixed-parameter schemes fail
2Measurement precision
If multiple read operations are performed to ensure decoding accuracy, then the measurement precision improves, but the access time increases and productivity decreases
Solution Approach 1:
The patent applies partial action by reading only the necessary number of bits (MSBs and conditionally LSBs) for each memory cell based on its state. Instead of performing multiple complete read operations on all cells, the system performs a first partial read of MSBs for all cells, then performs additional partial reads of LSBs only for the subset of cells that require verification, significantly reducing total access time while maintaining decoding accuracy
Solution Approach 2:
The reading mechanism uses the information obtained from MSB reading to self-determine which cells require additional LSB reading. The system automatically identifies cells with uncertain states based on MSB patterns and directs subsequent reading resources only to those cells, eliminating the need for blanket multiple read operations across the entire memory array
Data Source
AI summary
The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.