Two-Pass Programming for QLC Flash Memory Cells

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Solution Overview

Problem

Multi-bit flash memory devices, such as quad-level cell (QLC) flash NAND memory devices, face challenges in programming accuracy and time due to large floating gate-floating gate coupling and the need for multiple programming passes, which can result in increased programming time and accuracy degradation.

Innovation Solution

A two-pass programming procedure is employed, where the first pass includes N blanket pulses without verify operations to place intermediate coarse states, and the second pass includes N Program and Verify (PV) pulses to achieve accurate programming, reducing programming time and improving accuracy by minimizing verify operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple programming passes are used to program multi-bit flash memory cells, then programming accuracy is improved, but programming time increases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The programming process is divided into two distinct passes: a first pass that applies N blanket pulses without verify operations to place intermediate coarse states, and a second pass that applies N program and verify (PV) pulses to achieve accurate final programming. This segmentation allows the system to balance speed and accuracy by performing coarse programming quickly followed by precise verification-based programming.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If verify operations are performed during programming, then programming accuracy is improved, but programming time increases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Verify operations are applied partially - only in the second programming pass after intermediate states have been established by blanket pulses in the first pass. This partial application of verification maintains necessary accuracy while minimizing the time penalty associated with frequent verify operations.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of time

If blanket pulses are applied without verify operations, then programming time is reduced, but programming accuracy deteriorates

Engineering Contradiction:
Improveprogramming timeVSAvoidprogramming accuracy
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

Blanket pulses without verify operations are applied as a preliminary action in the first programming pass to establish intermediate coarse states. This preliminary programming creates a foundation that reduces the burden on the second pass, allowing the final accurate programming to be achieved more efficiently with verify operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10217515B2Programming memory devices
Publication Date: 2019.02.26 INTEL NDTM US LLC
  • US10217515B2 patent drawing
  • US10217515B2 patent drawing
  • US10217515B2 patent drawing

AI summary

Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.