QLC Memory Maintenance Using Stored ECC Data Between Two Passes
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Solution Overview
Problem
Two-pass write operations in quad-level cell (QLC) memory systems can cause damage and reduce reliability due to extended voltage application and increased latency from repeated read operations, leading to uncorrectable errors and reduced memory system performance.
Innovation Solution
Implement a two-portion maintenance operation where the controller stores data from the first error control operation in a portion of the memory system, such as SLC blocks or volatile memory, and uses this data during the second portion to reduce latency and increase reliability by skipping redundant error control operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-pass write operations are used in QLC memory systems, then data can be written to multi-level cells, but extended voltage application causes damage and reduces reliability
Solution Approach 1:
The patent segments the write operation into two distinct passes: a first pass that writes data to QLC memory cells using a first voltage distribution, and a second pass that writes the same data using a second voltage distribution. This segmentation allows the system to perform necessary write operations while distributing voltage stress across separate events, thereby reducing cumulative damage to individual memory cells and improving overall reliability.
2Reliability
If repeated read operations are performed during two-pass write operations, then data can be verified and corrected, but latency increases due to extended operation time
Solution Approach 1:
The patent performs error control operations and data verification during the first pass write operation, before the second pass is executed. By preliminarily checking and correcting data in the first pass, the system reduces the need for repeated read operations during the second pass, thereby maintaining data integrity while minimizing additional latency.
3Quantity of substance
If voltage is applied for extended duration to program QLC states, then data can be stored in quad-level cells, but memory cell damage increases
Solution Approach 1:
The patent divides the voltage application process into two separate passes with different voltage distributions. Instead of applying a single extended voltage pulse that would cause cumulative damage, the system applies voltage in two distinct events with intermediate recovery time, allowing memory cells to withstand the total voltage exposure required for QLC programming while reducing peak stress and damage accumulation.
Data Source
AI summary
Methods, systems, and devices for multi-level cell maintenance operations are described. A controller of a memory device may perform a two-portion maintenance operation in order to transfer data from a first block of memory cells to a second block of memory cells. For example, during a first portion of the maintenance operation, the controller may read first data from the first block of memory cells and perform a first error control operation to correct the first data. The controller may store second data associated with the first error control operation to volatile memory of the memory device in response to performing the first error control operation. During a second portion of the maintenance operation, the controller may perform a second error control operation using the second data associated with the first error control operations stored to the volatile memory of the memory device.