QLC Memory Programming with Grouped Verify and Bit Line Bias
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Solution Overview
Problem
The increasing demand for higher storage densities in flash memory, particularly in Quad-Level Cell (QLC) architecture, leads to longer programming times due to additional programming processes, necessitating a reduction in programming time.
Innovation Solution
Implementing a method where memory cells are grouped by adjacent program states and verified with a common verify voltage, followed by applying a pre-determined number of program pulses with specific bit line bias voltages to reduce cell-to-cell variation and narrow the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC architecture is implemented to increase storage density, then storage capacity is improved, but programming time increases
Solution Approach 1:
The patent segments memory cells into different groups based on their target program states (first group for first program state, second group for second program state). This segmentation allows different programming strategies to be applied to different groups simultaneously, reducing overall programming time while maintaining QLC storage capacity
Solution Approach 2:
The patent applies a preliminary verification step before programming to identify which memory cells need programming and their target states. This preliminary action enables optimized programming pulse sequences to be predetermined, reducing the number of programming iterations needed and thus reducing programming time
2Quantity of substance
If additional programming processes are applied to achieve higher storage density, then storage capacity is improved, but programming complexity increases
Solution Approach 1:
The patent divides the programming process into distinct phases: verification phase (identifying cells needing programming) and programming phase (applying optimized pulses). This segmentation simplifies the control logic by separating identification from programming actions
Solution Approach 2:
The patent uses different programming pulse parameters (voltage levels, pulse widths) for different memory cell groups based on their target program states. This parameter optimization simplifies the programming process by using standardized pulse sequences for each group rather than complex adaptive control
3Ease of operation
If conventional programming methods are used, then programming process is simple, but cell-to-cell variation in threshold voltage distribution is high
Solution Approach 1:
The patent applies different bit line bias voltages to different bit lines during programming based on the specific requirements of memory cells in each group. This local quality adjustment compensates for cell-to-cell variations and improves threshold voltage distribution uniformity while maintaining overall process simplicity
Solution Approach 2:
The patent incorporates verification steps that provide feedback on programming status. Based on verification results, the system can adjust programming parameters or re-program cells that did not reach the target state, improving threshold voltage distribution uniformity without significantly increasing operational complexity
Data Source
AI summary
A method of operating a memory device includes applying a first program voltage to a selected word line corresponding to a target group of memory cells, applying a first verify voltage to the selected word line corresponding to the target group of memory cells, applying a pre-determined number of program pulses to the selected word line corresponding to a second memory cell of the target group of memory cells, and applying a first bit line bias voltage to a first bit line corresponding to the second memory cell of the target group of memory cells during applying a first or a last of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell.