QLC Memory Programming With Consecutive Coarse-Fine Operations
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Solution Overview
Problem
Existing memory devices face challenges in minimizing cell-to-cell interference during programming, leading to degraded read window margins and increased read bit error rates, particularly in quad-level cell (QLC) memory, due to the use of coarse-fine programming algorithms that require significant SLC buffering, thereby incurring additional hardware costs.
Innovation Solution
A modified coarse-fine programming algorithm that initiates with a smaller number of threshold voltage (Vt) distributions, followed by consecutive coarse and fine programming operations, reducing the need for SLC buffering and minimizing Vt shifts, thus enhancing read window margins and reducing program noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If coarse-fine programming algorithm is used, then programming precision is improved, but hardware cost increases due to additional SLC buffering requirements
Solution Approach 1:
The patent segments the programming process into distinct phases (initial programming with first set of Vt distributions, then coarse programming with second set, then fine programming with third set). This segmentation allows each phase to use optimized buffering strategies, reducing the need for extensive SLC buffering while maintaining programming precision.
Solution Approach 2:
The patent performs preliminary programming operations to establish initial Vt distributions before executing the coarse-fine programming algorithm. This preliminary action prepares the memory cells in a state that reduces the buffering requirements during subsequent coarse and fine programming phases, thereby reducing hardware costs while maintaining precision.
2Manufacturing precision
If consecutive coarse and fine programming operations are performed, then read window margin is improved, but programming time increases
Solution Approach 1:
The patent implements periodic action by alternating between coarse programming operations and fine programming operations in a structured sequence. This periodic approach allows the system to achieve improved read window margins through multiple passes while managing programming time through efficient alternation between coarse and fine programming phases.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that each programming phase (initial, coarse, fine) builds upon the previous phase without unnecessary interruptions. The consecutive programming operations are designed to flow continuously, with each phase preparing the memory cells for the next phase, thereby minimizing idle time while achieving improved read window margins.
3Device complexity
If modified coarse-fine programming algorithm is used, then hardware cost is reduced, but program noise may increase
Solution Approach 1:
The patent incorporates feedback mechanisms where the results of initial programming and coarse programming are used to adjust and optimize the fine programming phase. This feedback allows the system to maintain low program noise levels even with reduced SLC buffering, as the programming parameters are continuously optimized based on previous phase results.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting programming voltage levels, pulse widths, and other critical parameters across the different programming phases. These parameter changes are optimized to minimize program noise while reducing hardware requirements, allowing the system to achieve both cost reduction and noise control.
Data Source
AI summary
A memory device includes a memory array having memory cells associated with wordlines. Control logic, operatively coupled with the memory array, causes a first set of memory cells, associated with a first wordline of the memory array, to be programmed with a first set of threshold voltage distributions. After a second set of memory cells, associated with a second wordline that is adjacent to the first wordline, has been programmed, the control logic causes the first set of memory cells to be further coarse programmed with an intermediate third set of threshold voltage distributions that is greater in number than the first set of threshold voltage distributions. The control logic causes the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions.