QLC Memory Controller Adaptive Threshold Voltage Adjustment
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Solution Overview
Problem
As storage apparatus capacity increases, the reliability of memory cell transistors in quad-level cell (QLC) systems decreases due to narrower threshold voltage distributions and changes in threshold voltages.
Innovation Solution
A memory system with a memory controller that writes, reads, and measures errors in data stored in memory cell transistors, adjusting the difference between adjacent threshold voltage distributions based on measured error numbers to improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-valuation is used to increase storage capacity in QLC, then storage capacity increases, but reliability decreases due to narrower threshold voltage distributions
Solution Approach 1:
The patent implements dynamic adjustment of write distribution intervals based on measured error rates. The memory controller monitors error rates for different bit values and dynamically modifies the threshold voltage distribution intervals for subsequent write operations, transitioning from static to adaptive write parameters to optimize both capacity utilization and reliability
Solution Approach 2:
The system establishes a feedback loop where error rates are measured during read operations and used to adjust write distribution intervals for future operations. The memory controller continuously monitors error rates for adjacent bit values and uses this feedback information to dynamically optimize the threshold voltage distributions, creating a closed-loop control system that adapts to actual memory performance
2Quantity of substance
If threshold voltage distributions are narrowed to increase storage capacity, then more data can be stored, but error rates increase due to smaller voltage margins
Solution Approach 1:
The patent changes the write distribution interval parameter dynamically based on measured error rates. When error rates for specific bit value transitions are high, the system adjusts the threshold voltage distribution intervals for those transitions in subsequent write operations, optimizing the voltage margins to reduce errors while maintaining high storage density
Solution Approach 2:
The system applies different write distribution intervals to different bit value transitions based on their individual error characteristics. Instead of using a uniform interval for all 16 threshold voltage levels, the patent selectively adjusts intervals for specific adjacent bit value pairs (e.g., 0→1, 2→3, 4→5) based on their measured error rates, optimizing performance locally for each transition
Data Source
AI summary
A memory system includes a memory device including a plurality of memory cell transistors, and a memory controller. The memory controller is configured to write data to each of the plurality of memory cell transistors, the data having one of a plurality of bit values, read the data from the plurality of memory cell transistors, and measure a number of errors included in the read data with respect to two of the bit values of which corresponding threshold voltage distributions are adjacent to each other. The memory controller is further configured to adjust a difference between the threshold voltage distributions corresponding to the two of the bit values based on the measured number of errors.