QLC Memory Error-Rate Adjustment for Selective Error Correction

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Solution Overview

Problem

Conventional memory systems face inefficiencies in programming operations due to high error rates and bandwidth bottlenecks, leading to increased latency and cost when correcting errors in quad-level cell (QLC) memory, particularly in two-pass programming processes.

Innovation Solution

The system determines error rates for data stored in QLC memory cells and provides data to the controller only when the error rate exceeds a threshold, reducing the number of input/output operations and eliminating bottlenecks by using error correction operations on high-error data during the second programming pass.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction operations are performed on all data in conventional memory systems, then data reliability is improved, but bandwidth saturation and latency increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidbandwidth efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by performing error correction operations selectively on specific data portions (first data from first pages) rather than uniformly on all data. The controller determines whether to perform error correction based on local error characteristics, applying correction only where needed while leaving other data unchanged, thus optimizing bandwidth usage while maintaining reliability where required.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements partial action by performing error correction on only a subset of data that requires it, rather than applying correction to all data. This selective approach avoids the excessive bandwidth consumption that would result from universal error correction, while still achieving sufficient reliability for the critical data portions that are corrected.

Inventive Principle:
Principle #16Partial or excessive action

2Productivity

If buffer memories are added to eliminate bandwidth bottlenecks, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improvebandwidth efficiencyVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling the controller to autonomously determine which data requires error correction and perform corrections in-place during the programming process. This eliminates the need for external buffer memories to temporarily store data, as the controller manages its own error correction needs using existing resources, thereby avoiding increased hardware complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent extracts the error correction function from a separate hardware buffering stage and integrates it directly into the controller's programming operation. By taking out the need for dedicated buffer memory and embedding error correction capability within the controller's existing architecture, the system maintains productivity improvements without adding hardware complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If level misplacements are minimized through selective error correction, then reliability is improved, but the number of input/output operations increases

Engineering Contradiction:
Improvelevel placement accuracyVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing error correction on the first data from the first pages during the first programming pass, before the second programming pass occurs. This preliminary correction prevents level misplacements that would otherwise require time-consuming corrections in later passes, thereby improving reliability while minimizing the total programming time through proactive error handling.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3762812B1Providing data of a memory system based on an adjustable error rate
Publication Date: 2025.07.30 MICRON TECHNOLOGY INC
  • EP3762812B1 patent drawingFigure 1
  • EP3762812B1 patent drawingFigure 2
  • EP3762812B1 patent drawingFigure 3

AI summary

A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.