QLC Memory Encoding to Avoid Inter-Cell Interference Patterns
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Solution Overview
Problem
Quadruple-level cell (QLC) memory devices face inter-cell interference issues due to programming high program-voltage levels adjacent to low levels, leading to errors and read performance degradation, which existing encoding schemes fail to adequately address without significant rate loss or increased read operations.
Innovation Solution
A memory system employing a constrained encoding scheme with a first encoder jointly encoding two data bits for selected logical pages using a constrained code and a second encoder independently encoding remaining data bits using an error-correction code to generate symbols for program-voltage levels, thereby avoiding interference-prone sequences and minimizing additional sensing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional encoding schemes are used for QLC memory cells, then device complexity is low, but inter-cell interference causes errors and read performance degradation
Solution Approach 1:
The encoding scheme is segmented into two distinct encoders: a first encoder that jointly encodes data bits from multiple logical pages using a constrained code, and a second encoder that independently encodes the remaining data bits using an error-correction code. This segmentation allows each encoder to specialize in addressing specific aspects of the interference problem while maintaining overall system reliability.
Solution Approach 2:
The first encoder performs preliminary encoding of data bits from multiple logical pages using a constrained code that prevents harmful patterns before the data is written to adjacent memory cells. This preliminary action proactively eliminates the root cause of inter-cell interference rather than attempting to correct errors after they occur.
2Reliability
If joint encoding of multiple logical pages is performed, then harmful patterns are avoided, but additional sensing operations are required
Solution Approach 1:
The constrained code is designed to apply encoding only to the extent necessary to prevent harmful patterns, rather than requiring complete re-encoding of all data. The first encoder processes only the data bits that would create harmful patterns when adjacent cells are programmed, while the second encoder handles the remaining bits with standard error-correction coding.
3Quantity of substance
If higher program-voltage levels are programmed adjacent to lower levels, then storage capacity is maximized, but inter-cell interference increases
Solution Approach 1:
The constrained code in the first encoder applies preliminary anti-action by preventing the programming of harmful patterns where high program-voltage levels are adjacent to low levels. The encoder proactively identifies and eliminates bit combinations that would create such harmful voltage adjacencies before the programming operation occurs, thereby counteracting the interference problem in advance.
Data Source
AI summary
Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a constrained encoding device including a first encoder and a second encoder. The first encoder jointly encodes, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages. The second encoder independently encodes, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.