QLC Memory Programming Loop Control for Interference Reduction
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Solution Overview
Problem
Quad-level cell (QLC) memory technology faces limitations in endurance and I/O performance due to multi-pass programming requirements, which lead to programming interference and difficulties in accurately identifying stored data states, especially with smaller voltage windows.
Innovation Solution
Implementing a control circuit that manages multiple programming loops to optimize programming operations, including a foggy-fine programming scheme and dynamic voltage adjustments, to improve programming efficiency and reduce interference between memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-pass programming is used to program QLC memory cells, then programming completeness is improved, but programming time and I/O performance deteriorate
Solution Approach 1:
The patent applies preliminary action by receiving and buffering data for subsequent memory blocks during the last programming loop of the current block. This allows the system to prepare the next programming operation in advance, so that when the current programming completes, the next block's data is already ready to be transferred, eliminating idle waiting time and improving overall programming throughput.
2Measurement precision
If multiple programming loops are executed to ensure accurate data state identification, then data state accuracy is improved, but programming interference increases
Solution Approach 1:
The patent implements periodic action through structured programming loops with systematic voltage adjustments. Each programming loop applies specific pass voltages to word lines in a periodic sequence, allowing memory cells to be programmed in controlled stages. This periodic structure enables accurate data state identification while managing interference by resetting and reapplying voltages in organized cycles rather than continuous uncontrolled programming.
3Quantity of substance
If voltage windows are reduced to increase storage density, then storage capacity is improved, but data state identification difficulty increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting pass voltages during different programming loops. The control circuit modifies voltage levels applied to word lines based on the programming stage and detected data states. This allows the system to maintain sensitivity for identifying data states even when voltage windows are reduced, as the adjustable voltage parameters can be optimized for each specific programming condition and memory cell state.
Data Source
AI summary
A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.