QLC Memory Pre-program Pass for Buffer Reduction
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Solution Overview
Problem
Quad-level cell (QLC) memory programming requires significant cache buffer resources due to high bit error rates after coarse programming, leading to increased costs and space challenges as sub-blocks of memory cells are added.
Innovation Solution
A pre-program pass is performed using multi-level cell (MLC) logical states to reduce the demand for cache buffer resources by programming the extra page and lower page bits of QLC logical states, allowing only the top and upper page bits to be stored in the cache buffer, and adjusting the target voltage levels to minimize bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QLC memory is programmed with coarse programming, then programming speed is improved, but bit error rate increases leading to higher cache buffer requirements
Solution Approach 1:
The patent segments the 4-bit QLC programming task into two parts: first programming 2 bits (MLC mode) and then programming the remaining 2 bits. This segmentation allows the system to achieve faster programming speeds by using MLC programming for the first 2 bits while maintaining reliability by only buffering the critical 2 least significant bits in cache, thus resolving the contradiction between programming speed and bit error rate.
Solution Approach 2:
The patent applies preliminary action by first programming the 2 most significant bits to MLC logical states before programming the remaining 2 bits. This preliminary MLC programming establishes a reliable base state that reduces the burden on cache buffer resources during subsequent programming operations, thereby improving overall programming efficiency while maintaining data reliability.
2Reliability
If cache buffer size is increased to handle QLC programming, then bit error rate is reduced, but cost and space requirements increase
Solution Approach 1:
The patent extracts only the 2 least significant bits that require buffering in cache memory, while the 2 most significant bits are programmed directly to MLC logical states without buffering. This extraction approach minimizes cache buffer requirements from 4 bits to 2 bits per page, significantly reducing cost and space while maintaining sufficient reliability for QLC programming.
3Quantity of substance
If MLC logical states are used for pre-programming, then cache buffer requirements are reduced, but programming complexity increases
Solution Approach 1:
The patent utilizes the existing MLC programming functionality of the memory device to program the first 2 bits, leveraging the multi-functionality of the same programming infrastructure. This approach reduces cache buffer requirements without requiring entirely new programming mechanisms, thereby limiting the increase in programming complexity while achieving significant buffer reduction.
Data Source
AI summary
A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.