Memory Controller Targeted Protection for QLC Data Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices, such as SSDs used as system disks, face performance degradation due to frequent read operations on quadruple level cell (QLC) blocks, which have shorter lifetimes and are less reliable than triple level cell (TLC) blocks, leading to data errors and increased error handling times, thereby reducing overall performance.
Innovation Solution
A method and apparatus for data management in memory devices using targeted protection control, where a memory controller monitors read counts and error bit counts to initiate a targeted protection procedure when thresholds are reached, preventing data damage from host device reading behaviors by relocating or remapping data to maintain storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC blocks are used to increase storage capacity, then storage capacity is improved, but data reliability deteriorates
Solution Approach 1:
The patent segments the storage system into different block types (QLC and TLC) with different reliability characteristics. By dividing the storage capacity into multiple blocks and selectively using QLC or TLC blocks based on data importance and access patterns, the system achieves high storage capacity while maintaining data reliability through heterogeneous block management.
Solution Approach 2:
The patent applies local quality by assigning different protection levels and block types to different data regions. Frequently accessed or critical data is stored in more reliable TLC blocks or protected with enhanced error correction, while less critical data uses QLC blocks for maximum capacity efficiency. This localized quality differentiation resolves the contradiction between capacity and reliability.
2Speed
If frequent read operations are performed on QLC blocks, then data accessibility is improved, but data errors increase
Solution Approach 1:
The patent implements dynamic block management where the system continuously monitors read counts and error rates of QLC blocks. Based on this monitoring, the system dynamically adjusts protection levels, migrates frequently accessed data to TLC blocks, or activates enhanced error correction mechanisms. This dynamic adaptation allows the system to maintain fast data accessibility while preventing data errors from excessive reads.
Solution Approach 2:
The patent employs feedback mechanisms through read count monitoring and error detection. When a QLC block exceeds a threshold of read operations or shows error signs, the system receives feedback and triggers protective actions such as data migration to more reliable blocks or activation of remedial measures. This feedback loop ensures data accessibility is maintained while preventing error accumulation from frequent reads.
3Reliability
If error handling mechanisms are activated, then data protection is improved, but system performance deteriorates
Solution Approach 1:
The patent applies preliminary action by proactively monitoring read counts and predicting when QLC blocks may develop errors before they actually occur. Based on predicted error risk, the system preemptively migrates data to TLC blocks or activates protection mechanisms. This preliminary action prevents errors while avoiding the performance penalty of continuous error handling, as protection is activated only when and where needed.
Solution Approach 2:
The patent implements partial error handling by applying protection mechanisms selectively rather than universally. Instead of activating comprehensive error handling for all blocks (which would degrade performance), the system applies enhanced protection only to specific QLC blocks that show signs of wear or are frequently accessed. This partial action maintains data protection for at-risk data while preserving system performance for other operations.
Data Source
AI summary
A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.