QLC NAND Memory Controller Soft Bit Read Level Shifting
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in accurately reading data due to changes in the quantity of charges retained in memory cells over time, leading to data value errors, as the read voltage techniques developed are not effective in addressing these changes.
Innovation Solution
A memory system comprising a NAND flash memory and a memory controller that acquires and decodes information from multiple pages, using a combination of hard bit and soft bit read operations with adjusted read levels to minimize bit error rates and correct errors, including a method of shifting read levels to optimize data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read voltage techniques are used, then the reading process is simple, but data read errors increase due to charge quantity changes over time
Solution Approach 1:
The read operation is segmented into multiple stages: hard bit read for initial data retrieval, followed by soft bit reads at multiple adjusted voltage levels for error correction. This segmentation allows the system to balance simplicity and accuracy by handling different error scenarios at different stages.
Solution Approach 2:
The read voltage levels are dynamically adjusted based on the detected error patterns. The system performs reads at multiple voltage levels (e.g., Vread1, Vread2, Vread3) and uses the results to correct errors, making the read process adaptive rather than static.
2Measurement precision
If multiple read operations with adjusted read levels are performed, then bit error rates are minimized and errors are corrected, but the read process becomes more complex
Solution Approach 1:
The system uses feedback from hard bit read results to guide soft bit read operations. Error detection results from initial reads trigger subsequent reads at adjusted voltage levels, creating a feedback loop that improves accuracy while managing complexity through conditional execution.
Solution Approach 2:
The read voltage parameter is changed across multiple read operations. By performing reads at different voltage levels (Vread1, Vread2, Vread3) and combining the results, the system achieves higher measurement precision without requiring a complete redesign of the read architecture.
3Reliability
If read levels are shifted to optimize data retrieval, then data read errors are reduced, but the control mechanism becomes more complex
Solution Approach 1:
The system performs preliminary hard bit reads before soft bit reads to establish baseline data and error patterns. This preliminary action allows subsequent voltage adjustments to be targeted and efficient, reducing the overall control complexity by preparing the system in advance.
Solution Approach 2:
The read operations are structured as periodic cycles: hard bit read, soft bit read at Vread1, soft bit read at Vread2, and so on. This periodic structure simplifies control by establishing a repeating pattern that can be managed through state machines or control logic.
Data Source
AI summary
According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE, UPPER, and HIGHER pages from a NAND memory 100 that includes QLCs each being capable of retaining a 4-bit value. An ECC circuit 260 of a memory controller 200 decodes the acquired HB information and SB1 to SB4 information on the four pages.