QLC NAND Symbol-Based Coding for Retention Error Correction
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Solution Overview
Problem
The increase in bits per cell and data retention times in QLC NAND flash memories degrades the ECC performance, particularly due to slow electrical charge degradation and voltage read accuracy issues, leading to increased bit error rates over time.
Innovation Solution
Implementing non-binary low-density parity-check (LDPC) codes with symbol-based encoding and decoding, and using asymmetric crossover probabilities by constraining the mapping of symbols to voltage levels, which improves ECC performance by utilizing soft information and optimizing the order of symbol-voltage level mappings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If four bits are stored in a single cell to increase storage density, then storage capacity is improved, but reliability deteriorates due to increased bit error rates
Solution Approach 1:
The patent changes the fundamental parameter of data representation from binary (bits) to non-binary (symbols with 4 or more levels). By encoding data as symbols rather than individual bits, the system achieves better error correction capability while maintaining high storage density. The non-binary LDPC codes operate on symbols, allowing the system to correct errors more effectively in QLC NAND flash where 4 bits per cell creates vulnerability to errors.
2Duration of action of stationary object
If data retention time is increased for cold storage applications, then storage duration is improved, but measurement precision deteriorates due to voltage read accuracy issues
Solution Approach 1:
The patent introduces soft information as an intermediary between the physical voltage levels and the decoded data. Instead of directly reading binary values from voltage levels, the system uses soft information (log-likelihood ratios) that capture the probability distribution of possible symbol values. This intermediary allows the decoder to account for voltage degradation over time while still accurately recovering the original data, effectively bridging the gap between deteriorating physical signals and reliable data retrieval.
Solution Approach 2:
The patent performs preliminary encoding using non-binary LDPC codes before storing data in the flash memory. This pre-encoding with enhanced error correction capability prepares the data to withstand the effects of long-term storage and voltage degradation. The asymmetric crossover probability modeling also performs preliminary characterization of error patterns, allowing the decoder to be pre-configured for optimal error correction under cold storage conditions.
3Reliability
If non-binary encoding and decoding procedures are used to improve ECC performance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the encoding and decoding process into distinct functional blocks: symbol mapping to voltage levels, non-binary LDPC encoding, storage, non-binary LDPC decoding, and symbol remapping to bits. Each block performs a specific function, making the overall complex system manageable and implementable. The segmentation also allows for optimized implementation of each component, such as using asymmetric crossover probability models specifically in the decoding stage without complicating the encoding process.
4Measurement precision
If asymmetric crossover probabilities are used by constraining symbol to voltage level mapping, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent deliberately introduces asymmetry in the mapping between symbols and voltage levels. Instead of using symmetric mapping where adjacent symbols map to adjacent voltage levels with equal probability, the system uses asymmetric crossover probabilities that reflect the actual physical characteristics of flash memory. This asymmetry allows the decoder to more accurately model error patterns and improve symbol error rate performance, while the mapping constraints keep the implementation complexity manageable by limiting the number of possible mappings.
Data Source
AI summary
Techniques for processing bits associated with an “N” multiple level cell NAND flash memory, such as a QLC NAND flash memory, are described. In an example, a system generates a symbol based on the bits. The symbol corresponds to at least two bits. The system encodes the symbol in a non-binary codeword and stores the non-binary codeword in the “N” multiple level cell NAND flash memory based on a mapping between symbols and voltage levels of the “N” multiple level cell NAND flash memory. The system initializes a non-binary decoding procedure based on asymmetric crossover probabilities between the voltage levels. The asymmetric crossover probabilities are defined based on the mapping between the symbols and the voltage level. The system decodes the non-binary codeword based on the non-binary decoding procedure.