QLC NAND Memory Two-Stage Programming for Buffer and Error Balance
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Solution Overview
Problem
The increasing memory capacity and cost of write buffers in three-dimensional NAND flash memory controllers due to simultaneous 4-bit data writing, along with the issue of inter-cell interference and biased bit error rates in quadruple level cell (QLC) technology, necessitate a solution to reduce write buffer capacity while maintaining reliability.
Innovation Solution
A memory system with a nonvolatile memory that stores 4-bit data using sixteen threshold regions and a controller that executes two-stage programming, allocating data to specific threshold regions to minimize inter-cell interference and reduce write buffer requirements, employing 1-4-5-5 coding to distribute boundaries for bit determination, thereby reducing the write buffer amount and minimizing bit error rate bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 4-bit data is written simultaneously to multiple memory cells to improve productivity, then the write buffer capacity and memory controller cost increase significantly
Solution Approach 1:
The patent segments the 4-bit data writing process into two separate stages: first writing to even-numbered memory cells, then writing to odd-numbered memory cells. This segmentation allows the write buffer to hold only 2 bits of data at a time instead of 4 bits, reducing the write buffer capacity requirement by half while maintaining simultaneous writing productivity.
2Quantity of substance
If data is written in two stages to reduce write buffer amount, then inter-cell interference is avoided, but bit error rate becomes largely biased
Solution Approach 1:
The patent applies local quality by assigning different boundary numbers to different bit positions within the 4-bit data. Specifically, the first and second bits use boundary number 1, while the third and fourth bits use boundary number 3. This localized differentiation balances the bit error rates across all four bits, preventing the large bias that would otherwise occur with uniform two-stage writing.
3Reliability
If boundary numbers are increased to reduce bit error rate bias, then writing speed decreases due to more threshold regions required
Solution Approach 1:
The patent changes the parameter of boundary numbers from uniform (all bits using the same boundary number) to differentiated (different bits using different boundary numbers). By setting boundary numbers to 1 for the first two bits and 3 for the last two bits, the patent achieves balanced bit error rates without requiring an excessive number of threshold regions, thus maintaining writing speed while improving reliability.
Data Source
AI summary
A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.