Memory Control Circuit Unit Balancing Write Volumes for QLC NAND Efficiency
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Solution Overview
Problem
The data write efficiency of memory storage apparatuses using quad level cell (QLC) NAND-type flash memory modules is reduced due to the odd number of memory dies, leading to inconsistent data writing speeds among memory units.
Innovation Solution
A data storing allocation method that determines initial write volumes and compensation data volumes based on the number of dies in each memory unit, allowing for balanced data distribution by transferring data according to the calculated volumes and speeds, ensuring that memory dies are kept busy simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC NAND-type flash memory modules with odd number of memory dies are used to meet basic memory capacity requirements, then memory capacity can be achieved, but data write efficiency is reduced due to inconsistent data writing speeds among memory units
Solution Approach 1:
The patent dynamically adjusts the write volume allocated to each memory unit based on its data writing speed. Memory units with faster writing speeds are assigned larger write volumes, while those with slower speeds receive smaller volumes. This parameter adjustment ensures that all memory units complete their write operations simultaneously, maximizing data write efficiency while maintaining the required memory capacity
Solution Approach 2:
The system implements dynamic write volume allocation that adapts to the real-time performance characteristics of each memory unit. By continuously monitoring data writing speeds and adjusting the distribution of write data accordingly, the system optimizes the utilization of all memory units, ensuring they remain busy simultaneously without idle waiting time
Data Source
AI summary
A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.