QLC Parity Mapping for Weak Word Line Error Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems using quad-level cells (QLCs) experience higher error rates due to weak word lines, leading to rapid wear and reduced performance, which can be exacerbated by techniques that retire blocks with these lines.
Innovation Solution
A memory system generates parity information for data stored in a set of one or more QLCs using a mapping between a first set of single-level memory cells and a second set of multi-level memory cells, and a second set of multi-level memory cells (e.g., QLCs), and a second set of parity information for the data and the parity information to the first set of single-level memory cells. The memory system 110 may support transferring data, with corresponding parity information, from lower-level memory cells to higher-level memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in QLCs to increase storage density, then storage capacity is improved, but error rate increases and reliability deteriorates
Solution Approach 1:
The patent segments data storage into two parts: original data stored in QLCs and generated parity information stored in SLCs. This segmentation allows the system to benefit from the high storage density of QLCs while using the high reliability of SLCs to protect against errors, thus resolving the contradiction between storage capacity and reliability.
Solution Approach 2:
The patent introduces parity information as an intermediary element that mediates between the high-capacity QLCs and the requirement for data reliability. The parity information, stored in reliable SLCs, acts as a protective layer that enables error detection and correction for data originally stored in QLCs, thereby maintaining reliability while preserving storage capacity benefits.
2Reliability
If blocks with weak word lines are retired to reduce errors, then reliability is improved, but memory device wear increases and lifespan decreases
Solution Approach 1:
The patent changes the parameter of data protection by introducing parity information with different error correction capabilities. Instead of retiring blocks with weak word lines, the system modifies the data storage parameters by storing parity information in SLCs, which have better error correction properties, thus maintaining reliability without reducing memory device lifespan.
3Reliability
If parity information is generated and stored for QLC data, then reliability is improved, but processing time and complexity increase
Solution Approach 1:
The patent applies preliminary action by generating and storing parity information in SLCs at the time of initial data writing. This upfront preparation eliminates the need for time-consuming error correction operations during data retrieval, as the parity information is already in place to protect the QLC data, thus reducing processing time delays.
4Productivity
If data is transferred from SLCs to QLCs to optimize storage, then storage efficiency is improved, but data integrity may be compromised due to QLC errors
Solution Approach 1:
The patent segments the data transfer process by maintaining a duality: original data resides in QLCs for efficient storage while generated parity information is stored in SLCs for integrity protection. This segmentation ensures that data can be efficiently transferred to QLCs without compromising integrity, as the SLC-stored parity serves as a safeguard against QLC errors.
Data Source
AI summary
Methods, systems, and devices for techniques to manage parity information for data transfer operations are described. A memory system may produce additional parity information for data to be stored in a set of multi-level memory cells. The memory system may receive a command to store data and may determine whether a destination physical address for the data includes a weak word line using a mapping. The memory system may generate parity information for the data using a mapping between a first set of single-level memory cells and a second set of multi-level memory cells configured to store multiple bits of data. The memory system may store the data and the parity information to the first set of single-level memory cells and may transfer the data and the parity information from the first set of single-level memory cells to the second set of multi-level memory cells.