QLC NAND Cell Programming With Split-Bit Writes and Boundary Coding
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Solution Overview
Problem
In NAND flash memory systems, particularly with quadruple level cell (QLC) technology, there is a challenge in reducing the write buffer capacity of the memory controller while avoiding inter-cell interference and minimizing the bit error rate, especially in three-dimensional memory structures.
Innovation Solution
The implementation of a memory system with a nonvolatile memory that uses 16 threshold regions to store 4-bit data, where the memory controller executes two distinct programs to write data, optimizing the number of boundaries used for determining bit values to reduce interference and error rates, and employing 1-4-5-5 data coding to minimize the write buffer requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 4-bit data is written simultaneously to multiple memory cells to avoid inter-cell interference, then data reliability is improved, but write buffer capacity requirements increase
Solution Approach 1:
The patent divides the 4-bit data writing process into two separate stages: first writing bits 0-1, then writing bits 2-3. This segmentation allows the system to complete writing to one set of memory cells before moving to the next, eliminating the need to hold all 4-bit data in the write buffer simultaneously, thereby reducing write buffer capacity requirements while maintaining data reliability.
Solution Approach 2:
The patent performs preliminary writing of the first two bits (0-1) to memory cells before writing the remaining bits (2-3). This preliminary action enables the system to complete the first stage of data writing and release buffer resources before committing to the second stage, effectively reducing the peak write buffer capacity needed while ensuring data integrity through sequential completion.
2Quantity of substance
If data is written in two stages to reduce write buffer capacity, then write buffer requirements are reduced, but bit error rate bias increases
Solution Approach 1:
The patent applies different writing strategies to different bit positions within the 4-bit data. Bits 0-1 are written in the first stage while bits 2-3 are written in the second stage. This local differentiation allows the system to manage write buffer capacity efficiently for each bit group while applying optimized writing parameters specific to each stage, thereby reducing bit error rate bias that would otherwise result from uniform two-stage writing.
3Quantity of substance
If three-dimensional NAND memory is used to increase memory capacity, then storage density is improved, but write buffer cost increases
Solution Approach 1:
The patent segments the data writing operation into two distinct phases, writing bits 0-1 first and then bits 2-3. This segmentation enables three-dimensional NAND memory to achieve high storage density without requiring a proportionally large write buffer in the memory controller, as each phase completes before the next begins, thereby reducing memory controller cost while maintaining increased memory capacity.
Data Source
AI summary
A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.