Dynamic Data Relocation Between QLC and pSLC Memory Regions
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Solution Overview
Problem
Multilevel storage techniques in memory systems increase data capacity but often result in slower reading and writing speeds due to the use of multibit data storage, which can hinder performance.
Innovation Solution
A memory system that moves frequently accessed data from a slower QLC (Quad-Level Cell) region to a faster pSLC (pseudo Single-Level Cell) region based on read request frequency, utilizing a management table to track and manage data movement, thereby optimizing reading speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel storage technique is used to increase memory capacity, then storage capacity increases, but reading speed and writing speed decrease
Solution Approach 1:
The memory system is segmented into two distinct storage regions: a first storage region (QLC) for high-capacity multibit data storage and a second storage region (pSLC) for high-speed frequently accessed data. This segmentation allows the system to simultaneously achieve high storage capacity in the QLC region while providing fast access speeds in the pSLC region, resolving the contradiction between capacity and speed.
Solution Approach 2:
Different storage regions are assigned different functional qualities: the QLC region is optimized for high-density storage with 4 bits per cell, while the pSLC region is optimized for high-speed read/write operations with 1 bit per cell. This local differentiation of quality allows each region to excel at its specific function, resolving the speed-capacity tradeoff.
2Quantity of substance
If data is stored in QLC region for high capacity, then storage efficiency increases, but access speed decreases
Solution Approach 1:
The memory controller performs preliminary actions by monitoring read request frequencies and proactively moving frequently accessed data from the QLC region to the pSLC region before it is actually needed. This predictive data movement ensures that hot data is already in the high-speed region when access is requested, eliminating the speed penalty of QLC storage for frequently accessed data.
Solution Approach 2:
The system implements a feedback mechanism where the memory controller continuously monitors read request frequencies for data stored in the QLC region. Based on this feedback information, the controller automatically decides which data to move to the pSLC region, creating a dynamic adaptation system that optimizes performance based on actual access patterns.
3Quantity of substance
If frequently accessed data remains in QLC region, then storage capacity utilization is maximized, but reading speed deteriorates
Solution Approach 1:
The data placement in the memory system is made dynamic rather than static. The memory controller continuously monitors access patterns and dynamically adjusts data location by moving frequently accessed data from QLC to pSLC. This dynamic adaptation allows the system to maintain high capacity utilization in QLC for cold data while providing fast access for hot data in pSLC, resolving the contradiction between capacity utilization and reading speed.
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile memory array with a plurality of memory cells. Each memory cell is a multilevel cell to which multibit data can be written. The non-volatile memory array includes a first storage region in which the multibit data of a first bit level is written and a second storage region in which data of a second bit level less than the first bit level is written. A memory controller is configured to move pieces of data from the first storage region to the second storage region based on the number of data read requests for the pieces of data received over a period of time or on external information received from a host device that sends read requests.