QLC-to-TLC Cell Block Transfer for Read Disturb Control

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Solution Overview

Problem

Higher-level cell blocks in memory devices, such as QLC blocks, experience longer read times and higher raw bit error rates due to charge loss and read disturb, leading to performance degradation in read-intensive workloads.

Innovation Solution

Performing a higher-level-to-lower-level cell block transfer, such as QLC-to-TLC, based on a read count threshold, transferring data from QLC blocks to TLC blocks to reduce read times and improve bit error rates, using a read count-based block transfer mechanism.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in higher-level cell blocks (QLC), then storage capacity is improved, but read time increases and bit error rate increases due to charge loss and read disturb

Engineering Contradiction:

Improvestorage capacityVSAvoidread performance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent dynamically switches cell blocks between higher-level (QLC) and lower-level (TLC) modes based on workload characteristics. When read-intensive workloads are detected, QLC blocks are converted to TLC mode to improve read performance. This dynamic adaptation allows the system to optimize between storage capacity and read reliability depending on actual usage patterns

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of memory cell blocks by altering the voltage thresholds and read levels. When converting from QLC to TLC mode, the system adjusts the read voltage levels and threshold distributions to match TLC characteristics, thereby improving read accuracy and reducing bit error rates while maintaining the same physical hardware

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If higher-level cell blocks are used, then storage density is improved, but read disturb and charge loss increase leading to higher bit error rates

Engineering Contradiction:

Improvestorage densityVSAvoidbit error rate

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a buffer or intermediate storage mechanism where data from QLC blocks can be temporarily relocated when read disturb becomes problematic. This intermediary approach allows the system to maintain high storage density in QLC blocks while providing a fallback path through TLC-mode blocks when error rates increase, effectively mediating between density and reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If read count increases in higher-level cell blocks, then workload capacity is improved, but read time and error rate increase due to read disturb

Engineering Contradiction:

Improveworkload capacityVSAvoidread time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by proactively converting QLC blocks to TLC mode before read performance degrades significantly. By monitoring workload patterns and preemptively adjusting cell block modes, the system avoids the performance penalty of high read counts in QLC blocks, maintaining optimal read times even under heavy workload conditions

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250298518A1Higher-level-to-lower-level cell block transfer based read count

Publication Date: 2025.09.25 MICRON TECHNOLOGY INC

AI summary

Various embodiments provide for performing a higher-level-to-lower-level cell block transfer (e.g., quad-level cell (QLC)-to-triple-level cell (TLC) block transfer) on a higher-level cell block (e.g., a QLC block) of a memory device based on a read count of the higher-level cell block, where the memory device can be part of a memory system, such as a memory sub-system.