QLC/TLC Die Smart Verify for Faster Multi-Bit Programming
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Solution Overview
Problem
Existing memory systems face challenges in determining which states to verify after a program pulse in multi-bit per cell modes, leading to potential over-programming or inefficient use of time, current, and power.
Innovation Solution
The memory system employs a smart verify technique that counts the number of memory cells with a threshold voltage above a verify voltage for certain states, skipping verification of other states until a sufficient number of cells meet the threshold, thereby optimizing the verify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If verification of all target states is performed after each program pulse, then programming precision is improved, but programming time and power consumption increase
Solution Approach 1:
The patent applies partial verification by selectively verifying only certain target states after each program pulse rather than all states. The verify operation determines whether to perform verification based on the current program pulse characteristics, skipping verification for states that are unlikely to be reached, thereby reducing programming time while maintaining sufficient programming precision.
Solution Approach 2:
The verification process is segmented into selective verification of different target states. Instead of a uniform verification approach for all states, the patent divides the verification task by identifying and verifying only the relevant subset of states that need checking after each program pulse, reducing overall verification overhead.
2Manufacturing precision
If verification of all target states is performed after each program pulse, then programming precision is improved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by performing partial verification of target states rather than complete verification of all states. The verify operation selectively determines which states require verification based on program pulse characteristics, eliminating unnecessary power expenditure on verifying states that cannot be reached with the current programming level.
3Productivity
If verification of target state is skipped after program pulse, then programming time is reduced, but over-programming occurs
Solution Approach 1:
The patent implements feedback-based selective verification where the verify operation uses feedback from program pulse characteristics and memory cell state information to determine which target states require verification. This feedback mechanism ensures that verification is performed only when necessary to prevent over-programming, while skipping verification for states that are safely not yet reached, thus balancing speed and precision.
4Manufacturing precision
If verification of target state is performed too early in programming process, then programming precision is maintained, but time and power are wasted
Solution Approach 1:
The patent applies preliminary analysis through the verify operation that assesses program pulse characteristics before deciding whether to perform verification. This preliminary action determines in advance which target states are likely to be reached with the current or upcoming program pulses, allowing the system to skip unnecessary early verifications and only perform verification when it becomes relevant, thus avoiding wasted time and power.
Data Source
AI summary
Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.