QLC Memory Voltage Level Selection for Charge Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory sub-systems, particularly in quad-level cell (QLC) memory blocks, charge leakage leads to disparate voltage shifts across different portions of the block over time, causing default read threshold levels to fail, resulting in high bit error rates and degraded performance, especially in mobile applications where space is limited.
Innovation Solution
The memory cell voltage level selection component dynamically sets the read threshold level of QLC memory blocks to the voltage threshold level of the last successful read operation, accounting for differences in charge loss across different portions of the block, thereby mitigating failed reads and improving data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a default read threshold level is used for QLC memory blocks, then the memory sub-system can operate with simple control logic, but charge leakage causes disparate voltage shifts across different portions of the block over time, leading to failed reads and high bit error rates
Solution Approach 1:
The patent implements dynamic voltage level selection by adjusting the read threshold voltage based on the time elapsed since the last write operation. The voltage level selection component selects from multiple voltage levels (first voltage level for recent writes, second voltage level for older writes) based on temporal characteristics, making the system adaptive to charge leakage over time without requiring complex per-cell tracking
Solution Approach 2:
The patent changes the voltage parameter dynamically based on time elapsed since write operations. By monitoring the time duration and selecting appropriate voltage levels from a set of predefined levels, the system adapts to charge leakage effects without complex control logic, resolving the contradiction between reliability and simplicity
2Quantity of substance
If data is migrated over extended time periods in QLC memory blocks, then more data can be stored, but disparate voltage shifts occur across different portions of the block, causing default read thresholds to fail
Solution Approach 1:
The patent applies dynamic voltage adjustment based on the time period since write operations. When data is migrated over extended periods, the voltage level selection component automatically selects appropriate voltage levels from multiple available levels based on the elapsed time, ensuring reliable reads across all portions of the memory block regardless of when data was written
Solution Approach 2:
The patent performs preliminary voltage level selection based on anticipated time delays. By pre-selecting appropriate voltage levels based on the expected time period since write operations, the system prepares the read threshold in advance to accommodate charge leakage that will occur during extended storage periods, preventing read failures before they happen
3Quantity of substance
If mobile applications with limited space use QLC memory blocks, then storage density is improved, but charge leakage causes performance degradation due to voltage shifts
Solution Approach 1:
The patent implements dynamic voltage level selection specifically optimized for mobile applications. The voltage level selection component adjusts read thresholds based on time elapsed since writes, maintaining high data retrieval performance in space-constrained mobile devices that use QLC memory for increased storage density
Solution Approach 2:
The patent changes voltage parameters dynamically to maintain performance in mobile applications. By selecting from multiple voltage levels based on temporal characteristics of data access patterns, the system maintains high productivity despite the charge leakage inherent in high-density QLC memory used in space-limited mobile devices
Data Source
AI summary
A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.