Memory Subsystem Write Bandwidth Control for QLC Consistency

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Solution Overview

Problem

Denser memory media like QLC experience inconsistent write performance due to varying programming times for sequential write operations, leading to noticeable performance spikes and variance in write bandwidth utilization.

Innovation Solution

A performance management process is implemented that identifies long sequential writes and adjusts bandwidth utilization by monitoring and managing write patterns, ensuring they meet performance targets through a performance manager component, while excluding non-host initiated operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If denser memory media like QLC are used to increase storage capacity, then storage density is improved, but write performance consistency deteriorates due to varying programming times

Engineering Contradiction:
Improvestorage densityVSAvoidwrite performance consistency
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system dynamically adjusts the issuance rate of host write commands based on monitored write bandwidth utilization. When write operations are detected to be slower than a threshold, the system reduces the rate of new write command issuance to prevent performance degradation, thereby maintaining consistent write performance while using high-density QLC media.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors write bandwidth utilization and compares it against a threshold to detect performance variance. Based on this feedback, the system adjusts the write command issuance rate in real-time, creating a closed-loop control system that maintains write performance consistency despite the inherent variability of QLC programming times.

Inventive Principle:
Principle #23Feedback

2Productivity

If write bandwidth utilization is increased to improve productivity, then write speed is improved, but performance variance increases leading to inconsistent write performance

Engineering Contradiction:
Improvewrite speedVSAvoidperformance consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically controls the write command issuance rate based on real-time monitoring of write bandwidth utilization. By adjusting the rate of write command issuance in response to measured performance, the system maintains optimal write speed while preventing the performance variance that would result from excessive or uncontrolled write bandwidth utilization.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of write command issuance rate based on monitored write bandwidth utilization. When performance variance is detected, the system modifies this parameter to maintain consistent write performance, effectively trading off raw write speed for performance consistency when necessary.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11455107B2Managing sequential write performance consistency for memory devices
Publication Date: 2022.09.27 MICRON TECHNOLOGY INC
  • US11455107B2 patent drawing
  • US11455107B2 patent drawing
  • US11455107B2 patent drawing

AI summary

A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.