QLC Flash Write Management Using Reliability-Based Block Conversion
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Solution Overview
Problem
Quadruple-level cell (QLC) flash memory faces challenges with higher error rates and slower read/write speeds due to its higher storage density, necessitating advanced write management mechanisms to enhance performance and endurance.
Innovation Solution
A block management and configuration mechanism for QLC flash memory that includes block reconfiguration and selective conversion modes based on block reliability examination, along with strategic garbage collection operations to optimize performance and lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC flash memory is used to increase storage density, then storage capacity is improved, but read and write speeds deteriorate and error rates increase
Solution Approach 1:
The patent divides the flash memory into different regions (QLC region and TLC region) with different cell types. The QLC region provides high storage density while the TLC region maintains faster read/write speeds, allowing the system to segment the storage function to achieve both high capacity and acceptable performance.
Solution Approach 2:
Different regions of the flash memory are assigned different qualities - the QLC region uses quad-level cells for maximum density where performance requirements are lowest, while the TLC region uses triple-level cells for better performance where needed, creating local optimization of cell types based on functional requirements.
2Quantity of substance
If QLC flash memory is used to increase storage density, then storage capacity is improved, but reliability deteriorates due to higher error rates
Solution Approach 1:
The memory is segmented into QLC and TLC regions, allowing critical data to be stored in the more reliable TLC region while less critical data uses the higher-density QLC region, thereby maintaining overall system reliability while achieving high storage capacity.
Solution Approach 2:
The patent implements a wear leveling mechanism that monitors and tracks the wear status of different blocks, dynamically adjusting write operations to distribute wear evenly and prevent any single block from failing, thereby maintaining reliability over the device's operational life.
3Productivity
If garbage collection operations are performed frequently to maintain performance, then write performance is improved, but device lifespan deteriorates
Solution Approach 1:
The patent dynamically adjusts the garbage collection threshold based on the wear status of the flash memory. When wear is low, a higher threshold allows fewer GC operations to preserve lifespan; when wear increases, the threshold decreases to maintain performance, creating a dynamic balance between productivity and durability.
Solution Approach 2:
The system changes the garbage collection threshold parameter based on wear status. By adjusting this parameter dynamically, the system can reduce GC frequency when wear is low (preserving lifespan) while ensuring GC occurs when necessary (maintaining performance), resolving the contradiction between these two goals.
Data Source
AI summary
A method of controlling a flash memory includes: in response to a host write command, writing host data associated with the host write command into a target block of a region of the flash memory in a specific write mode with one-shot programming; performing a block reliability examination on the target block of the region to generate a block reliability indication; selecting one of a direct conversion mode and a garbage collection-based conversion mode according to the block reliability indication; and performing a cell level reconfiguration with respect to the target block according to the selected conversion mode.