QoS-Based Core Mapping for Low-Latency Packet Processing

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Solution Overview

Problem

Existing electronic devices face latency issues in processing data packets due to the application processor's inability to handle packets with different quality of service (QoS) requirements, particularly for low-latency services like URLLC, as they are delayed by normal packets during merging.

Innovation Solution

The application processor shares group information based on QoS characteristics with the communication processor, mapping packets to corresponding cores for parallel processing, reducing latency by configuring sessions to specific cores based on QoS.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If packets are merged in the order received from the communication processor, then packet processing follows a simple sequential approach, but low-latency service packets (e.g., URLLC) are delayed by normal packets

Engineering Contradiction:
Improvepacket processing latencyVSAvoidpacket processing complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments packets into different groups based on QoS characteristics and processes them through different cores. Low-latency service packets are separated from normal packets and handled by dedicated cores, eliminating delays caused by sequential processing of all packets together.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The application processor preliminarily configures group information and mapping relationships between packet groups and cores before packet processing begins. This pre-configuration enables immediate routing of packets to appropriate cores based on their QoS requirements, reducing processing latency without requiring complex real-time decisions.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple packets are processed through a single control core, then the processing logic is simple, but the processing speed and throughput are limited

Engineering Contradiction:
Improvepacket processing throughputVSAvoidcore coordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple packet processing functions across multiple cores, allowing parallel processing of different packet groups. By combining the processing capabilities of multiple cores and assigning different packet groups to different cores, the system achieves higher throughput while maintaining manageable complexity through systematic packet distribution.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new dimension of parallel processing by utilizing multiple cores simultaneously. Instead of processing packets sequentially through a single core, the system distributes packets across multiple cores in parallel, significantly increasing processing throughput while the mapping mechanism keeps coordination complexity manageable.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If all packets are processed through the same core, then resource management is simple, but QoS requirements of different services cannot be met

Engineering Contradiction:
ImproveQoS guarantee reliabilityVSAvoidsession configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning specific packet groups with particular QoS requirements to specific cores optimized for those requirements. Low-latency service packets are routed to cores configured for fast processing, while normal packets are handled by other cores, ensuring that each packet group receives the appropriate processing quality needed for its service requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The mapping module provides a universal mechanism that works across different packet groups and service types. By establishing a general mapping relationship between packet groups and cores that can accommodate various QoS requirements, the system achieves reliable QoS guarantees for multiple services while using a unified management approach rather than service-specific configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12537772B2Electronic device, and method for processing received data packet by electronic device
Publication Date: 2026.01.27 SAMSUNG ELECTRONICS CO LTD
  • US12537772B2 patent drawing
  • US12537772B2 patent drawing
  • US12537772B2 patent drawing

AI summary

An electronic device is provided. The electronic device includes an application processor comprising a plurality of cores, and a communication processor electrically connected to the application processor. The application processor may configure at least one session associated with respective applications based on quality of service (QoS) so as to correspond to at least one core from among the plurality of cores, transmit, to the communication processor, information corresponding to a first core configured for a first session from among the at least one session, receive a data packet of the first session from the communication processor, and process the received data packet of the first session by means of the first core configured for the first session, based on the information corresponding to the first core.