On-Chip QoS Engine for Data Packet Processing
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Solution Overview
Problem
Existing System on a Chip (SoC) technologies lack effective quality of service (QoS) management for data packets, particularly in small-scale systems, which is crucial for broadband applications and diverse data consumers, leading to inefficiencies in data handling and throughput.
Innovation Solution
An on-chip data packet processing method and integrated circuit with a wire-speed engine that adds metadata to data packets, forwards them to a QoS unit, and alters metadata, enabling efficient QoS management by determining priority and routing based on various metadata fields such as flow ID, session ID, and QoS-related fields, allowing for centralized QoS management and multipass handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QoS management is implemented for data packets in small-scale systems, then quality of service and data throughput are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple QoS management functions (classification, prioritization, scheduling, and packet handling) into a single integrated QoS engine that operates at wire speed. This consolidation improves data throughput while managing device complexity by unified multiple functions into one cohesive unit rather than separate components.
Solution Approach 2:
The patent implements preliminary classification and metadata assignment at the ingress port before packets enter the main processing pipeline. By pre-processing packets and assigning QoS metadata early in the flow, the system improves throughput efficiency while reducing the processing burden on downstream components, thereby managing overall device complexity.
2Productivity
If wire-speed processing with metadata addition is implemented, then data handling efficiency is improved, but power consumption increases
Solution Approach 1:
The patent replaces general-purpose software-based packet processing with specialized hardware components including a wire-speed engine and QoS engine implemented in ASIC or FPGA. This hardware substitution achieves wire-speed data handling efficiency while optimizing power consumption through dedicated circuitry that processes packets in parallel without the overhead of software interpretation.
Solution Approach 2:
The patent changes the operational parameters of packet processing by implementing fixed-function hardware logic that operates at wire speed with predetermined processing paths. This parameter change from flexible software processing to fixed hardware processing improves data handling efficiency while reducing dynamic power consumption through optimized circuit design.
3Reliability
If centralized QoS management is implemented, then quality of service control is improved, but processing time and latency increase
Solution Approach 1:
The patent performs preliminary classification, metadata assignment, and QoS parameter determination at the ingress port before packets enter the main switching fabric. This pre-processing ensures that centralized QoS management decisions are made in advance, improving QoS control reliability while minimizing actual processing time during packet forwarding.
Solution Approach 2:
The patent implements continuous wire-speed processing throughout the packet flow path, with the QoS engine operating continuously alongside the data plane. This eliminates idle processing cycles and ensures that QoS management actions are performed without interruption, maintaining both high service control reliability and low latency.
4Measurement precision
If metadata is added to data packets for QoS management, then routing and prioritization accuracy are improved, but device complexity increases
Solution Approach 1:
The patent implements a universal metadata structure that serves multiple QoS functions simultaneously including classification, prioritization, routing, and scheduling. This single metadata framework improves routing and prioritization accuracy while managing device complexity by using one multi-functional data structure rather than multiple separate tagging systems.
Data Source
AI summary
An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.