QOS Management Circuit for Data Bus Interface Priority Handling

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Solution Overview

Problem

Designers face challenges in implementing suitable data bus communication between different portions of a system, particularly in managing quality of service (QOS) due to varying bit formats and the complexity of interface circuitry in existing data bus protocols, which can lead to delays and incorrect processing of transactions.

Innovation Solution

A method and circuit for implementing QOS processing in a data bus interface, where input read/write commands with higher QOS values increase or decrease the QOS values of preceding or subsequent commands in a FIFO queue, allowing for priority management and efficient data bus operations, and includes a data bus interface circuit with a FIFO command queue, a QOS management circuit, and a command translation circuit to convert and manage QOS values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional data bus architectures (PCI, AMBA) are used with standard interface circuits, then communication between different portions of the system is enabled, but the complexity of interface circuitry increases and quality of service cannot be managed due to varying bit formats and protocol limitations

Engineering Contradiction:
Improvequality of service managementVSAvoidinterface circuitry complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A QOS management circuit is introduced as an intermediary component between the data bus interface and the processing elements. This circuit intercepts read/write commands, compares their QOS values, and dynamically adjusts the QOS of commands in the FIFO queue based on priority needs, enabling QOS management without requiring complex modifications to the entire interface circuitry

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system dynamically changes the QOS parameter of commands in the FIFO queue based on the priority of newly arrived commands. When a high-priority command arrives, the QOS values of subsequent commands are increased to ensure proper priority handling, allowing flexible QOS management adapt to varying communication needs

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple read/write commands are buffered in FIFO queue for burst mode transmission, then communication efficiency is improved, but delays occur in processing high-priority commands that arrive after low-priority commands

Engineering Contradiction:
Improvedata bus throughputVSAvoidcommand processing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The QOS management circuit continuously monitors the QOS values of commands in the FIFO queue and dynamically adjusts them based on newly arrived commands. This feedback mechanism ensures that high-priority commands can override lower-priority commands by increasing the QOS of subsequent commands, preventing indefinite delays while maintaining burst mode efficiency

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system transitions from a static FIFO processing order to a dynamic QOS-based priority system. The QOS values of commands are not fixed but can be changed during queue processing based on the arrival of new commands, allowing the system to adapt priority levels in real-time and minimize delays for high-priority operations

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If interface circuits are implemented to communicate data in different bit formats according to data bus protocol specifications, then communication compatibility is achieved, but the complexity of interface circuitry is further compounded for advanced communication functions

Engineering Contradiction:
Improvebit format compatibilityVSAvoidinterface circuitry complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The QOS management functionality is extracted as a separate, dedicated circuit module within the data bus interface. This specialized sub-circuit handles QOS comparison and adjustment operations independently, allowing the rest of the interface circuitry to focus on standard protocol compliance without the added complexity of QOS management logic

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8612648B1Method and apparatus for implementing quality of service in a data bus interface
Publication Date: 2013.12.17 XILINX INC
  • US8612648B1 patent drawing
  • US8612648B1 patent drawing
  • US8612648B1 patent drawing

AI summary

In one embodiment, a method for implementing quality of service (QOS) processing in a data bus interface. Each input read/write command is stored in a first-in-first-out queue. Each input read/write command includes a respective QOS value. In response to an input first read/write command having a QOS value higher than the QOS value of the read/write command at a head of the first-in-first-out queue, the QOS value of each of a first number of read/write commands is increased as each read/write command is removed from the head of the first-in-first-out queue.