QoS Packet Scheduling via Memory Interface for Cache Coherency

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Solution Overview

Problem

Existing high-performance packet processing systems face inefficiencies due to cache coherency issues and performance penalties when using multiple packet engines, particularly in network-load balancing and deep packet inspection, where sharing memory leads to cache invalidation and inefficient copy operations.

Innovation Solution

Implementing a QoS packet scheduling system that uses a classification tree to prioritize and schedule data packets without physically forwarding them to the QoS engine, allowing packet engines to process packets based on configuration information encoded in the packets themselves, thereby avoiding cache coherency issues and reducing the need for copy operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple packet engines share a central storage (memory or cache), then the QoS device can access all packets, but cache coherency issues cause cache contents to be undesirably invalidated

Engineering Contradiction:

ImproveQoS device access to packetsVSAvoidcache coherency

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a packet memory interface as an intermediary component between the packet engines and the central storage. This interface layer manages memory access and maintains cache coherency, allowing the QoS device to access packets without causing invalidation issues. The interface acts as a buffer and coordinator, resolving the conflict between shared access and cache reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the QoS device receives a copy of each packet from the packet engine, then the QoS device can process packets, but inefficient copy operations occur for each packet

Engineering Contradiction:

ImproveQoS packet processingVSAvoidcopy operation overhead

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent implements a selective copying mechanism where the QoS device receives packet data only when necessary, rather than copying every packet. The packet memory interface manages data transfer efficiently, copying packets only when the QoS device needs to access them for quality of service processing, thereby reducing unnecessary copy operations and associated energy overhead.

Inventive Principle:

Principle #26Copying

3Productivity

If multiple packet engines process packets in parallel on different cores or processors, then packet processing throughput increases, but cache coherency issues arise

Engineering Contradiction:

Improveparallel packet processing throughputVSAvoidcache coherency across cores

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the memory access architecture by introducing a packet memory interface that separates packet engine access from QoS device access. Each packet engine can access the central storage independently through the interface, which manages coherency protocols. This segmentation allows parallel processing on multiple cores while maintaining cache integrity through centralized interface control.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10084711B2High-performance quality-of-service packet scheduling for multiple packet processing engines

Publication Date: 2018.09.25 CITRIX SYSTEMS INC

AI summary

A system and method is provided for optimizing network traffic. The system includes a packet engine of a plurality of packet engines configured to acquire a data packet, to store the data packet in a queue, and to provide a request including a packet token representing the data packet, information regarding the size of the data packet, and a connection token. The system also includes a packet scheduler configured to receive the request; schedule the data packet using the connection token and the information regarding the size of the data packet; and provide the packet token and a notification to the packet engine for allowing the packet engine for transmitting the data packet.