QPP Interleaver Address Generation Without Multipliers or Dividers
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Solution Overview
Problem
The implementation of a Quadratic Permutation Polynomial (QPP) interleaver in turbo decoders for RF digital data transmissions requires significant hardware resources, leading to increased silicon area, power consumption, and reduced response time due to the need for multipliers and dividers in generating row and column addresses.
Innovation Solution
A hardware implementation using state machines to generate QPP interleaved row and column addresses, eliminating the need for multipliers and dividers, and leveraging previous addresses and data store dimensions to reduce processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional QPP interleaver implementation using multipliers and dividers is used, then accurate row and column address generation is achieved, but hardware footprint and power consumption increase significantly
Solution Approach 1:
The patent replaces the mechanical/mathematical system of multipliers and dividers with an electrical/digital system using state machines and lookup tables. The QPP interleaver function π(i) = [K1·i + K2·i²] mod K is implemented not through arithmetic computation but through pre-computed tables stored in memory, accessed via simple address calculation. This substitution eliminates complex arithmetic hardware while maintaining exact mathematical functionality.
Solution Approach 2:
The patent pre-computes and stores all possible QPP interleaver values in lookup tables during the design phase. The tables contain pre-calculated row and column addresses for all possible input positions. During operation, the system simply retrieves pre-computed values based on current position, avoiding real-time computation. This preliminary action transfers computational complexity from runtime to design time.
2Measurement precision
If multipliers and dividers are used for QPP address generation, then correct interleaving is achieved, but processing speed decreases due to computational complexity
Solution Approach 1:
The patent replaces slow arithmetic operations (multiplication and division) with fast memory access operations. The state machine generates simple address indices that directly index into pre-computed lookup tables. This substitution transforms a computationally intensive process into a simple memory retrieval process, dramatically increasing processing speed while maintaining exact interleaving correctness.
Solution Approach 2:
The patent creates copies of the QPP interleaver function in the form of lookup tables stored in memory. Instead of computing the function once and using the result, the function is copied into tabular form for all possible inputs. This allows O(1) retrieval time for any interleaver value, eliminating the need for repeated computation and significantly improving processing speed.
3Reliability
If conventional QPP interleaver is implemented, then proper data scrambling is achieved, but power consumption increases due to complex arithmetic operations
Solution Approach 1:
The patent replaces energy-intensive arithmetic operations with low-power memory access operations. The state machine requires minimal logic resources to generate address indices, and the actual interleaver values are retrieved from lookup tables using simple read operations. This substitution dramatically reduces dynamic power consumption while maintaining the exact same interleaving function, preserving error correction capability.
Solution Approach 2:
The patent extracts the computationally intensive QPP calculation from the runtime operation and moves it to the design phase. The complex arithmetic is performed once during table generation, and only simple address indexing remains during operation. This extraction separates the heavy computational burden from the low-power operational phase, reducing overall system power consumption.
Data Source
AI summary
A hardware implementation of a QPP interleaved address generator, or QPP interleaver, for use in a QPP turbo decoder uses state machines to determine BCJR engine QPP interleaved row and column addresses used by a soft-bit decoder operating in interleaved half-iteration alpha scan mode or interleaved half-iteration beta scan mode, as well as during non-interleaved half-iterations, if desired. Because QPP interleaving is pseudorandom in nature, the QPP address generator state machines leverage off knowledge of previous row/column addresses generated, as well as knowledge of the maximum row/column dimensions of the systematic soft-bit data store, to reduce the complexity of the processing performed. The described QPP address generator may be implemented in hardware with reduced hardware footprint, reduced power consumption, less heat production and an improved time response. Generated addresses may be provided to BCJR engines directly, or used to retrieve stored systematic soft-bits provided to the respective BCJR engines.