QPP Interleaver Address Generation With Iterative Modulo Increments
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The implementation of Quadratic Permutation Polynomial (QPP) interleavers in integrated circuits, such as FPGAs, faces challenges due to cumbersome multiplication and modulo operations required for address sequence computation, leading to large and high-latency circuits.
Innovation Solution
A method for address generation is introduced, involving the initialization of block size, skip value, and increment values, with iterative updates using modulo operations to generate a sequence of addresses efficiently, reducing circuit complexity and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Quadratic Permutation Polynomial interleavers are implemented using conventional multiplication and modulo operations, then the address sequence computation can be performed, but the circuit becomes large and high-latency
Solution Approach 1:
The patent transforms the quadratic permutation polynomial calculation by changing the computational parameters from direct multiplication and modulo operations to an iterative addition-based approach. The address sequence is generated by repeatedly adding increment values and taking modulo with the block size, rather than performing multiplication operations. This parameter transformation reduces circuit complexity while maintaining computational accuracy.
Solution Approach 2:
The patent replaces the mechanical multiplication operation with an equivalent addition-based computational mechanism. Instead of using multipliers and modulo units, the system uses adders and iterative increment operations to achieve the same mathematical result, thereby simplifying the hardware architecture and reducing latency.
2Reliability
If Quadratic Permutation Polynomial interleavers are implemented using conventional multiplication and modulo operations, then the address sequence computation can be performed, but the circuit latency is high
Solution Approach 1:
The patent changes the computational parameters from synchronous multiplication-based calculation to iterative addition-based calculation. By using incremental updates where each address is computed by adding a predetermined increment to the previous address and taking modulo with the block size, the system achieves lower latency while maintaining the correctness of the address sequence generation.
3Device complexity
If iterative address generation with modulo operations is used, then circuit complexity is reduced, but the block size and skip value management becomes more complex
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the increment values in a lookup table during the design phase. The initialization process simply retrieves these pre-computed increments based on the block size and skip value, rather than computing them in real-time. This shifts the complexity from operational to design-time, simplifying the actual circuit operation.
Data Source
AI summary
For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.