QPP Interleaver Address Generator With Simplified Modulo Circuit
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Solution Overview
Problem
Existing hardware implementations of quadratic permutation polynomial (QPP) interleavers for turbo-channel codes are inefficient due to complex multiplication and modulo operations, which hinder high-throughput encoding and decoding processes.
Innovation Solution
A simplified address generator circuit is developed, reducing the number of adders, subtractors, and registers, and eliminating selection operations, allowing for efficient address generation using only add, subtract, and select operations, and enabling pipelining for parallel processing of multiple sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex multiplication and modulo operations are used in QPP interleaver implementation, then address generation accuracy is maintained, but circuit complexity and processing time increase
Solution Approach 1:
The patent transforms the mathematical operations from complex multiplication and modulo to simplified addition and subtraction operations. Specifically, it uses the property that (a + b) mod K can be implemented as a + b - K when a + b >= K, replacing complex operations with simpler arithmetic that achieves the same result with reduced circuit complexity
Solution Approach 2:
The patent extracts and eliminates the complex multiplication and modulo operations from the QPP interleaver implementation, retaining only the essential addition and subtraction operations needed to achieve the interleaving function, thereby simplifying the overall circuit architecture
2Measurement precision
If complex multiplication and modulo operations are used in QPP interleaver implementation, then address generation accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent changes the operational parameters from complex multiplication and modulo to simple addition and subtraction, which are computationally less intensive and can be executed faster in hardware, thereby improving processing speed while maintaining the correctness of address generation through proper handling of the modulo condition
3Measurement precision
If more adders, subtractors, and registers are used in address generator, then address generation accuracy is improved, but resource consumption increases
Solution Approach 1:
The patent merges the functions of multiple adders and subtractors into fewer unified computational units. By combining the address generation logic and the modulo operation handling into integrated circuit blocks, it reduces the total number of discrete components while preserving the accuracy of address calculation
4Adaptability or versatility
If selection operations are included in address generation, then processing flexibility is improved, but circuit complexity increases
Solution Approach 1:
The patent removes complex selection operations from the address generation circuit, replacing them with direct conditional subtraction logic that achieves the same functional outcome without requiring additional multiplexers or selection logic, thereby reducing circuit complexity while maintaining processing flexibility
Data Source
AI summary
Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from −K to −1 for K a block size, and the second range is from 0 to K−1.