QPP Interleaver Address Generation Using Recursive Units
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Solution Overview
Problem
Existing QPP interleaver designs require significant memory capacity to store interleaver addresses, which is inefficient in terms of hardware complexity and memory usage, especially for varying decoding lengths in mobile communication systems like 3GPP LTE.
Innovation Solution
The proposed address generation apparatus and method utilize a recursive unit structure to directly compute and output interleaver addresses serially or in parallel based on the QPP function Π(i) = (f1i + f2i2) mod k, reducing the need for large memory tables by using a basic recursive unit and additional units to generate multiple sets of interleaver addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory or address table is used to store computed interleaver addresses in advance, then address lookup is simplified, but memory capacity and hardware complexity increase significantly
Solution Approach 1:
The patent extracts the address generation function from the memory storage function. Instead of storing pre-computed addresses in large memory tables, the system uses recursive units to generate addresses on-demand through computation. This separates the address generation logic from storage requirements, eliminating the need for large capacity memory while maintaining address lookup capability.
Solution Approach 2:
The patent replaces the mechanical/memory-based address storage system with a computational system using recursive units. The address generation is performed through mathematical recursion (Π(i) = (f1·i + f2·i²) mod k) rather than physical memory storage, substituting computational logic for hardware storage resources.
2Adaptability or versatility
If address table stores all possible interleaver addresses for varying decoding lengths, then adaptability to different code segment lengths is improved, but device complexity and memory requirements increase
Solution Approach 1:
The patent introduces dynamic configuration capability where the recursive units can be reconfigured for different code segment lengths through configurable parameters (k, f1, f2). Instead of static pre-stored tables for each length, the system dynamically adapts by adjusting recursion parameters, enabling support for varying decoding lengths without proportional increase in hardware complexity.
Solution Approach 2:
The patent uses parameter-based adaptation where changing the recursion parameters (information block length k, coefficients f1 and f2) allows the same hardware structure to generate addresses for different code segment lengths. This parameter-driven approach replaces the need for multiple dedicated address tables, reducing device complexity while maintaining versatility.
3Productivity
If parallel structure is used to generate multiple interleaver addresses simultaneously, then processing speed is improved, but the number of recursive units and hardware resources increase
Solution Approach 1:
The patent segments the parallel address generation into multiple recursive units, each responsible for generating a subset of addresses. This segmentation allows parallel processing while controlling hardware resources, as each unit handles a specific portion of the address space rather than requiring a single unit to generate all addresses sequentially.
Solution Approach 2:
The patent designs recursive units with universal functionality where each unit can be configured to generate different portions of the address sequence. The same recursive unit structure serves multiple purposes by adjusting configuration parameters, reducing the total number of dedicated units needed for parallel generation compared to having specialized units for each address range.
Data Source
AI summary
An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function Π(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein Π(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0≦i≦k−1.