QPP Turbo Interleaver Size Selection for Parallel Decoding

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Solution Overview

Problem

Existing turbo coding systems face challenges in efficiently defining contention-free interleavers for various information block sizes, leading to inefficiencies and potential memory access contentions during decoding, which affect the performance and scalability of communication systems.

Innovation Solution

A method and apparatus for selecting interleaver sizes for turbo codes, using a set of predefined sizes based on semi-log slicing, where the interleaver size is determined by factors such as K' = K" or K' = K" ± δ(K"), and employing permutations like π(i) = (iP0 + A + d(i))mod K' or π(i) = (f1 × i + f2 × i^2)mod K' to ensure contention-free interleaving, thereby allowing for flexible parallelism and efficient decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional turbo interleavers are used for various information block sizes, then decoding performance may be maintained, but memory access contentions occur and decoding speed decreases

Engineering Contradiction:
Improvedecoding speedVSAvoidmemory access contention
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameter of interleaver structure by adopting a systematic design where the interleaver size is directly related to the information block size K (e.g., K' = K or K' = K ± δ(K)). This parameter change ensures that the interleaver dimensions match the data dimensions, enabling parallel processing without memory access contentions and achieving high-speed decoding while maintaining good decoding performance through optimized filler bit placement

Inventive Principle:
Principle #35Parameter changes

2Productivity

If filler bits are added to match interleaver size, then contention-free interleaving is achieved, but the number of filler bits increases decoding complexity

Engineering Contradiction:
Improveparallel processing capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies partial action by adding only the minimum necessary filler bits to reach the target interleaver size K' rather than padding to a fixed large size. By using relationships like K' = K or K' = K ± δ(K) where δ(K) is small, the system achieves sufficient parallel processing capability while minimizing the number of filler bits and associated decoding complexity

Inventive Principle:
Principle #16Partial or excessive action

3Ease of manufacture

If interleaver size is fixed for all block sizes, then implementation is simplified, but efficiency decreases for varying block sizes

Engineering Contradiction:
Improveimplementation simplicityVSAvoidencoding efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent implements a dynamic interleaver size selection mechanism where the interleaver size K' is adaptively determined based on the information block size K through predefined relationships (K' = K, K' = K ± δ(K), or K' from semi-log slicing). This dynamic approach allows the system to efficiently handle varying block sizes while maintaining implementation simplicity through a structured set of size relationships

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP2493079B1Turbo-decoding with contention-free QPP interleavers
Publication Date: 2013.09.18 MOTOROLA MOBILITY LLC
  • EP2493079B1 patent drawingFigure 1~5
  • EP2493079B1 patent drawingFigure 2
  • EP2493079B1 patent drawingFigure 3~6

AI summary

Methods and apparatus for turbo encoding and turbo decoding are provided herein. During operation of the turbo encoder (101) or turbo decoder (304) the size of the turbo interleaver (201,401,402) is determined in dependence on the information block size and the appropriate interleaving parameters are selected. These parameters configure the turbo interleaver, which is a contention-free interleaver and which is based on either a quadratic permutation polynomial QPP interleaver or an almost regular permutation ARP interleaver. If the information block size does not match a supported interleaver size, then the information block is padded by means of filler bits insertion.