QPP Interleaver Initialization Using Stored Values for Faster Decoding
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Solution Overview
Problem
Existing interleaving methods in turbo coding, such as those used in 3GPP standards, require significant processing effort and hardware resources due to sequential calculation of interleaver addresses, which increases system latency and reduces throughput.
Innovation Solution
The method involves calculating initial values of parameters for QPP interleaving in advance and storing them for use by logic circuitry, allowing parallel calculation of interleaved order positions, reducing the need for sequential address calculation and extra logic resources, and enabling interleaving in a SISO decoder with a single buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential calculation of interleaver addresses is used, then interleaving can be performed with simple logic circuitry, but system latency increases and throughput decreases
Solution Approach 1:
The patent pre-calculates and stores initial values of parameters (such as g(0) and c) that are required for interleaver address calculation. By having these values prepared in advance and stored in memory, the logic circuitry can quickly retrieve them during operation without performing sequential calculations, thus reducing system latency while maintaining relatively simple circuitry design
Solution Approach 2:
The patent replaces the mechanical sequential calculation process with a memory-based retrieval system. Instead of using logic circuitry to sequentially compute interleaver addresses, the system substitutes this with pre-computed values stored in memory that can be quickly accessed, thereby reducing the computational burden on the logic circuitry and improving processing speed
2Device complexity
If sequential calculation of interleaver addresses is used, then hardware resources can be minimized, but throughput is reduced
Solution Approach 1:
The patent performs preliminary calculation of interleaver parameters offline and stores the results in memory. During actual turbo decoding operations, the logic circuitry simply retrieves these pre-computed values rather than calculating them sequentially, which significantly improves throughput while keeping the hardware resources relatively minimal
Solution Approach 2:
The patent introduces a memory component as an intermediary between the input data and the logic circuitry. This memory stores pre-calculated initial values that mediate the interleaving process, allowing the logic circuitry to operate more efficiently without requiring complex computational hardware, thus improving throughput without proportionally increasing hardware resources
3Speed
If extra logic resources are allocated for interleaver address calculation, then processing speed can be improved, but hardware complexity increases
Solution Approach 1:
The patent substitutes complex sequential calculation logic with a simpler memory retrieval mechanism. By pre-calculating and storing the necessary parameters, the system achieves faster processing speeds without requiring complex logic circuitry, thus improving speed while controlling hardware complexity
Solution Approach 2:
The patent creates copies of pre-computed parameter values and stores them in memory for quick access. Instead of having complex logic circuitry recalculate these values during operation, the system uses stored copies, which simplifies the hardware while maintaining high processing speed
Data Source
AI summary
An interleaver and method for interleaving are provided, where initialization values are pre-calculated and stored in memory. In one implementation, the method of interleaving includes: calculating in advance an initial value of at least one parameter for use by logic circuitry to initialize interleaving operation; storing the initial value of the at least one parameter as a stored initial value of the at least one parameter; and using the stored initial value of the at least one parameter with the logic circuitry to generate interleaved order positions for the set of data items. In one implementation, the interleaver includes: logic circuitry for generating interleaved order positions for the set of data items and memory coupled to the logic circuitry for holding an initial value of at least one parameter for use by the logic circuitry to initialize interleaving operation.