QPSK LDPC Bit Interleaver for 16200-Bit Burst Error Dispersion
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 3/15, using a specific permutation order for bit group-based interleaving, is designed to effectively distribute burst errors, compatible with QPSK modulation for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in selecting modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The patent applies segmentation by dividing the bit stream into blocks and performing interleaving at the block level rather than bit-by-bit. The LDPC codeword is divided into multiple blocks, and each block is interleaved independently using a block interleaver, which prevents burst errors from affecting the entire codeword and thereby resolves the performance degradation issue while maintaining bandwidth efficiency
Solution Approach 2:
The patent introduces a block interleaver as an intermediary component between the LDPC encoder and the modulation stage. This block interleaver acts as a mediator that redistributes bits in a way that breaks up burst errors into scattered individual errors, which can then be effectively corrected by the LDPC decoder, thus resolving the contradiction between bandwidth efficiency and error performance
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then the system can achieve excellent performance, but the device complexity increases due to the need for optimized designs
Solution Approach 1:
The patent applies parameter changes by providing specific optimized parameters for the block interleaver including block size, interleaving depth, and permutation patterns that are tailored to specific LDPC code rates and modulation schemes. These optimized parameters enable excellent error correction performance for each specific configuration without requiring a completely different interleaver design for each case
Solution Approach 2:
The patent applies local quality by designing the interleaver with different interleaving patterns and depths for different parts of the codeword or for different code rates. The interleaving strategy is locally optimized for each specific operating condition (code rate, modulation order) rather than using a single universal design, thereby achieving high performance for each specific case
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.