QPSK LDPC Bit Interleaver Using Bit-Group Permutation

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 4/15, using a specific permutation order for bit group-based interleaving, is designed to effectively distribute burst errors, compatible with QPSK modulation for next-generation broadcasting systems like ATSC 3.0.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation

Engineering Contradiction:

Improvesystem performanceVSAvoidburst errors

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The bit interleaver divides the LDPC codeword into multiple bit groups (180 groups of 360 bits each) and applies permutation to each group independently. This segmentation allows the interleaver to effectively distribute burst errors across different bit groups, preventing concentrated error patterns from overwhelming the error correction capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a specific permutation order that operates in the bit group dimension, transforming the one-dimensional sequential bit stream into a two-dimensional structure (bit groups × permutation positions). This dimensional transformation enables effective burst error distribution while maintaining system simplicity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the bit interleaver is optimized for specific modulation order and code parameters, then performance is maintained, but the device complexity increases

Engineering Contradiction:

Improveperformance maintenanceVSAvoidinterleaver design complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent optimizes the permutation order specifically for LDPC codes with length 64800 and code rate 4/15, combined with QPSK modulation. By tailoring the permutation parameters to match specific system configurations, the interleaver achieves optimal performance without requiring complex adaptive mechanisms.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The bit interleaver applies different permutation patterns to different bit groups based on their positions in the codeword. This localized optimization ensures that each bit group is appropriately interleaved for its specific context, improving overall performance while keeping the design systematic and manageable.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10326476B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and quadrature phase shift keying, and bit interleaving method using same

Publication Date: 2019.06.18 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.