QPSK LDPC Bit Interleaving for Burst Error Dispersion
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and a code rate of 2/15, using a specific permutation order for bit group-based interleaving, optimized for QPSK modulation, to effectively distribute burst errors in broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in selecting modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (each containing 360 bits) and performs interleaving at the bit group level rather than individual bit level. This segmentation approach maintains the flexibility of BICM while effectively distributing burst errors across different bit groups, preventing concentrated error patterns that would degrade performance.
Solution Approach 2:
The patent introduces a new dimension of interleaving operation by performing bit group-based interleaving instead of traditional bit-by-bit interleaving. This dimensional change in the interleaving granularity allows the system to maintain bandwidth efficiency while adding robustness against burst errors through the reorganization of bit groups according to a specific permutation order.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance is improved, but the device complexity increases due to the need for specific permutation orders and memory structures
Solution Approach 1:
The patent optimizes the interleaver for specific parameters (LDPC codeword length of 64800, code rate of 2/15, and QPSK modulation) by using a specifically designed permutation order. This parameter-specific optimization achieves excellent error correction performance while keeping the interleaver structure relatively simple through the use of two memories and a processor configured for these particular parameters.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.