QR Decomposition Circuitry with Reordered Gram-Schmidt Operations
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Solution Overview
Problem
Existing QR decomposition techniques face data dependency stalls due to floating point operations and internal dependencies, which cause delays in hardware and software implementations, especially in multicore processors and deeply pipelined environments.
Innovation Solution
The implementation of a modified Gram-Schmidt algorithm with reordered operations that eliminate square-root and division operations from the computations of r(k,k) and q(1:m, k) values, utilizing multiplication/addition and division/square-root circuitry in a programmable integrated circuit device, allowing for reduced data dependencies and improved precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the modified Gram-Schmidt technique is used for QR decomposition, then the decomposition can be performed, but data dependencies cause computation delays and stalls in hardware and software implementations
Solution Approach 1:
The patent computes r(k,k) values and stores them in a buffer before they are needed for subsequent calculations. This preliminary computation and storage eliminates the data dependency stall that would otherwise occur when waiting for r(k,k) to be ready, thereby improving computation speed while maintaining decomposition accuracy
Solution Approach 2:
The patent introduces a buffer as an intermediary storage element between the computation of r(k,k) and its usage in subsequent steps. This buffer decouples the computation stages, allowing them to proceed independently without stalling, thus resolving the productivity issue while preserving the reliability of the decomposition process
2Measurement precision
If floating point functions are used for computing r(k,k), then accurate results are obtained, but long latencies occur due to the complexity of these operations
Solution Approach 1:
The patent performs the floating point computation of r(k,k) in advance and stores the results in a buffer. This preliminary action allows the computationally intensive operation to be completed before it is needed, reducing the critical path latency while maintaining precision through accurate floating point calculation
Solution Approach 2:
The patent dynamically schedules the computation of r(k,k) to occur at optimal times based on data availability and downstream requirements. By flexibly timing the floating point operations and using buffers to manage data flow, the system minimizes latency impact while preserving computational precision
Data Source
AI summary
Circuitry for performing QR decomposition of an input matrix includes multiplication/addition circuitry for performing multiplication and addition/subtraction operations on a plurality of inputs, division/square-root circuitry for performing division and square-root operations on an output of the multiplication/addition circuitry, a first memory for storing the input matrix, a second memory for storing a selected vector of the input matrix, and a selector for inputting to the multiplication/addition circuitry any one or more of a vector of the input matrix, the selected vector, and an output of the division/square-root circuitry. On respective successive passes, a respective vector of the input matrix is read from a first memory into a second memory, and elements of a respective vector of an R matrix of the QR decomposition are computed and the respective vector of the input matrix in the first memory is replaced with the respective vector of the R matrix.