QRNG Chip Uniformity Testing for Faster Mass Production Screening

The patent divides the entropy source evaluation into two distinct phases: a comprehensive non-IID test phase for detailed quality assessment, and a rapid Final Test phase for mass production screening. The Final Test uses a simplified uniformity test with reduced data length (512KB-1024KB) to quickly identify defective chips, while the full non-IID test is performed only on selected samples or for certification purposes. This segmentation allows mass production to proceed with acceptable test times while maintaining quality assurance through periodic comprehensive testing.

The patent applies partial action by performing only the essential uniformity test in the Final Test phase, rather than executing all 17 non-IID test cases. The uniformity test checks whether the entropy source output distributes evenly across possible values, which is the most critical requirement for random number generators. By focusing on this single essential test with reduced data length, the patent achieves sufficient quality screening for mass production without the time cost of complete testing.

The patent performs preliminary comprehensive non-IID testing on a subset of chips or during development phases to establish baseline quality metrics and identify common defect patterns. This preliminary action allows the Final Test to be designed with reduced data length while maintaining adequate discrimination between good and defective chips, as the test parameters and thresholds are calibrated based on prior comprehensive testing data.

The patent implements a feedback mechanism where results from periodic comprehensive non-IID testing are used to adjust and optimize the Final Test parameters. As production progresses and more chips are tested, the system learns from accumulated data to refine the uniformity test thresholds and data length requirements, ensuring that the simplified test maintains its precision over time while continuing to enable high-speed mass production.

The patent segments the quality assurance process into two layers: a rapid screening layer (Final Test) that processes all chips quickly to eliminate obvious defects, and a comprehensive verification layer (non-IID test) that performs detailed analysis on a representative sample or all chips if needed. This segmentation enables mass production to achieve both high throughput and quality assurance by applying the appropriate test depth to each chip based on screening results.

The patent changes the test parameters dynamically based on production needs and quality requirements. For standard mass production batches, the Final Test with reduced data length and simplified uniformity checking is applied to all chips for rapid screening. For critical applications or when quality trends indicate potential issues, the system can switch to performing full non-IID tests on increased sample sizes, thus adapting the reliability level to match production conditions while managing total test time.