Quad Memory Cell Diode Steering for Sneak Path Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently addressing individual resistivity switching storage elements due to the layout of diodes and contacts, leading to unintentional activation of adjacent memory cells and sneak paths, which affects the ability to individually address and read memory cells.
Innovation Solution
The implementation of a diode steering element that is shared among multiple resistivity switching storage elements, with a larger diode area compared to the contact area, allows for a stronger current to be applied to a selected memory cell, and the use of a bypass notch and off-parallel layout of X and Y lines to reduce sneak paths and enhance individual addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional layout of diodes and contacts is used in three-dimensional memory devices, then the device structure is simpler to manufacture, but unintentional activation of adjacent memory cells and sneak paths occur, affecting individual addressing capability
Solution Approach 1:
The memory array is segmented into distinct blocks with isolated diode steering elements. Each diode is spatially separated and configured to control current flow to specific groups of storage elements, preventing current leakage to adjacent cells. This segmentation enables reliable individual addressing by ensuring that selected cells are the only ones with complete current paths.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical stack architecture. Diodes are positioned at different vertical levels and contact storage elements through vertically extending conductive paths. This dimensional change allows diodes to control current flow to specific storage elements without interfering with adjacent cells in the horizontal plane, eliminating sneak paths.
2Power
If diode area is increased to apply stronger current to selected memory cells, then current flow through intended cell is improved, but device area increases
Solution Approach 1:
Multiple diode steering elements are merged into a shared control structure where a single diode controls current flow to multiple storage elements through different conductive paths. This merging allows the same diode to provide strong current to selected cells while sharing the current control function across the array, reducing the total diode area required compared to having dedicated diodes for each cell.
Solution Approach 2:
Each diode steering element is designed to perform multiple functions: controlling current to different storage elements at various voltage levels, providing both selection and isolation functions simultaneously. This multi-functionality allows smaller diode areas to achieve the same current control capability that would require larger dedicated diodes in conventional designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables effective individual addressing and reading of memory cells by ensuring that current flows only through the intended resistivity switching storage element, reducing sneak paths and improving the reliability of memory cell operations.
Implementation Method 1
at least three resistivity switching storage elements
Implementation Method 2
a diode steering element that is shared among multiple resistivity switching storage elements
Data Source
AI summary
A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.