Quad-Pumped Address Bus Pin Reduction
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Solution Overview
Problem
Conventional microprocessor address bus configurations require a large number of pins and excessive power due to double-pumped transactions, which is problematic in applications with size and power constraints.
Innovation Solution
A quad-pumped address bus configuration that reduces the number of address signal group pins and power consumption by asserting address and request data in multiple phases of a clock cycle, allowing for mode switching between double-pumped and quad-pumped transaction modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double-pumped address bus configuration is used, then addressing functionality is maintained, but package size and power consumption increase
Solution Approach 1:
The patent applies periodic action by dividing the address bus operation into multiple phases within a single clock cycle. Instead of asserting all address signals simultaneously (double-pumped), the system asserts address signals in sequential phases (first phase, second phase, third phase, fourth phase), reducing peak power consumption while maintaining full addressing functionality through time-multiplexed signal assertion.
Solution Approach 2:
The patent segments the address bus transaction into multiple phases, with different address signal groups (first address signal group, second address signal group, third address signal group, fourth address signal group) being asserted in sequence during different phases of the clock cycle. This segmentation allows the system to maintain complete addressing capability while reducing the number of signals active simultaneously, thereby reducing power consumption and package size requirements.
2Reliability
If double-pumped address bus configuration is used, then addressing functionality is maintained, but number of pins increases
Solution Approach 1:
The patent segments address signals into multiple groups that are asserted in different phases. By time-multiplexing the assertion of address signal groups rather than asserting them all simultaneously, the system can use fewer physical pins while maintaining full addressing functionality. The segmented phase-based assertion reduces pin requirements compared to simultaneous double-pumped operation.
Solution Approach 2:
The patent introduces a time dimension to the address bus operation by implementing phased assertion within a single clock cycle. Instead of using more pins for simultaneous signal assertion (spatial dimension), the system uses time-multiplexed assertion across four phases, effectively trading spatial complexity (number of pins) for temporal organization (phased assertion sequence).
3Use of energy by stationary object
If quad-pumped mode is implemented, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The patent implements dynamics by making the address bus configuration adaptable between different operating modes. The system can dynamically select between conventional double-pumped mode and the new quad-pumped phased mode based on operational requirements. This dynamic capability allows the system to optimize for power consumption in quad-pumped mode while maintaining compatibility with existing double-pumped operations, managing complexity through controlled adaptability.
Solution Approach 2:
The patent creates a universal address bus interface that can operate in multiple modes (conventional double-pumped mode and quad-pumped phased mode). By designing the address bus configuration to support both operating modes, the system achieves multi-functionality that reduces power consumption in quad-pumped mode while maintaining compatibility with existing systems and applications that require double-pumped operation, thereby managing complexity through versatility.
Data Source
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AI summary
A microprocessor interface system including a system bus with a bus clock and a quad-pumped address signal group, and including multiple devices coupled to the system bus. Each device is configured to perform a quad-pumped transaction on the system bus in which multiple request packets are sequentially transferred via the address signal group during each of multiple phases of one cycle of the bus clock. The devices may include at least one microprocessor and one or more bus agents. In one embodiment, the first address data is multiplexed onto the address signal group during first and second request packets during a first phase of the bus clock cycle, and the second address data is multiplexed onto the address signal group during third and fourth request packets during a second phase of the bus clock cycle.