Quad-Switched Multibit DAC for Low-Distortion Sigma-Delta Feedback

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Solution Overview

Problem

The existing multibit sigma-delta modulator circuits face non-linearity issues due to mismatch in unit resistive DAC elements, leading to increased noise floor and harmonic distortion, which degrades the signal-to-noise ratio and signal-to-noise and distortion ratio (SNDR) due to inherent DAC non-linearity.

Innovation Solution

A quad signal generator circuit is introduced to control 2N−1 unit resistive DAC elements, ensuring that all logic states of the control signals remain constant for at least one cycle of the sampling clock, thereby reducing non-linearity and harmonic distortion by evenly actuating the DAC elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multi-bit quantization is used in the sigma-delta modulator, then resolution and sampling rate performance is improved, but DAC non-linearity and mismatch errors increase

Engineering Contradiction:
ImproveresolutionVSAvoidDAC non-linearity
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent segments the multi-bit DAC into multiple sub-DACs, each handling a portion of the quantization bits. This segmentation reduces the complexity and mismatch errors in each individual sub-DAC while maintaining the overall high resolution capability of the multi-bit quantization system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic element matching (DEM) techniques that dynamically change the activation state of DAC elements based on previous error measurements. By changing the operational parameters of the DAC elements in real-time, the system compensates for manufacturing mismatches and reduces non-linearity while preserving the resolution benefits of multi-bit quantization.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If data weighted averaging is used to correct DAC mismatch, then linearity is improved, but excess loop delay increases

Engineering Contradiction:
ImprovelinearityVSAvoidexcess loop delay
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent implements preliminary calibration of DAC elements during manufacturing or initialization, storing correction factors that are applied in real-time operation. This preliminary action eliminates the need for complex runtime calculations like data weighted averaging, thereby improving linearity without introducing excessive loop delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses lookup tables that store pre-computed correction data for each DAC element. Instead of performing real-time weighted averaging calculations, the system copies and applies pre-determined correction values, significantly reducing the computational delay while maintaining linearity correction effectiveness.

Inventive Principle:
Principle #26Copying

3Measurement precision

If higher sampling rate is used to achieve given resolution, then quantization noise is reduced, but device complexity and power consumption increase

Engineering Contradiction:
Improvequantization noise performanceVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements noise shaping with feedback mechanisms that redirect quantization noise to higher frequency bands where it can be filtered out. This feedback-based noise shaping allows the system to achieve high resolution performance at lower sampling rates, reducing device complexity and power consumption while maintaining excellent quantization noise performance in the signal band.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11152951B2Quad switched multibit digital to analog converter and continuous time sigma-delta modulator
Publication Date: 2021.10.19 STMICROELECTRONICS INT NV
  • US11152951B2 patent drawing
  • US11152951B2 patent drawing
  • US11152951B2 patent drawing

AI summary

A quad signal generator circuit generates four 2N−1 bit control signals in response to a sampling clock and a 2N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N−1 bit control signals. Outputs of the 2N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N−1 bit control signals such that all logic states of bits of the four 2N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N−1 bit thermometer coded signal.