Quadratic Phase Generator for Accurate CAZAC Ranging Chirps
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Solution Overview
Problem
Conventional generation of Zadoff-Chu sequences for spatial ranging operations in electronic devices with wireless circuitry often results in quantization errors and inaccuracies in distance estimation due to finite bandwidth of digital-to-analog converters.
Innovation Solution
Incorporating a quadratic phase generator with a switch and numerically controlled oscillator to produce an interpolated constant amplitude zero autocorrelation (CAZAC) sequence, which is then adjusted using a weighting factor to achieve a chirp with variable bandwidth, reducing frequency outliers and improving distance estimation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional Zadoff-Chu sequence generation is used, then the circuit implementation is simpler, but quantization errors occur and distance estimation accuracy deteriorates
Solution Approach 1:
The quadratic phase generator is divided into multiple integrator stages (first integrator stage, second integrator stage connected in series) and a switch component. Each stage performs a specific function in generating the interpolated CAZAC sequence, breaking down the complex sequence generation into manageable segments that reduce quantization errors while maintaining implementability.
Solution Approach 2:
The patent introduces a quadratic phase generator as an intermediary component between the simple sequence generator and the final CAZAC sequence output. This intermediary generates interpolated CAZAC sequences that serve as a bridge, improving accuracy without requiring complete redesign of the entire system.
2Measurement precision
If the DAC has finite bandwidth, then the hardware implementation is practical, but band edges are disturbed and measurement precision worsens
Solution Approach 1:
The patent implements a dynamically adjustable quadratic phase generator where the switch can be controlled to adjust the bandwidth of the generated sequence. The numerically controlled oscillator dynamically adjusts the phase progression, allowing the system to adapt to different bandwidth requirements while maintaining accuracy despite the DAC's finite bandwidth constraints.
Solution Approach 2:
The patent changes the phase parameter of the CAZAC sequence by introducing quadratic phase terms through the integrator stages. This parameter modification allows the sequence to be perfectly interpolated, compensating for the finite bandwidth effects of the DAC and improving spatial ranging accuracy.
3Reliability
If interpolation is applied to the CAZAC sequence, then frequency outliers are reduced, but the device complexity increases
Solution Approach 1:
The patent replaces complex signal processing operations with a dedicated quadratic phase generator circuit implemented in hardware. Instead of using software-based interpolation methods that would require significant processing power and memory, the invention uses a compact circuit with integrators and switches that directly generates the interpolated sequence, reducing overall system complexity while improving reliability.
Data Source
AI summary
An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.