Quadrature Delay Clock Buffer Chain for 40-50 GHz PLLs
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Solution Overview
Problem
Existing phased lock loop (PLL) designs face challenges in operating at frequencies above 34 GHz due to noise, parasitic capacitance, and narrow tuning range, limiting data rates to 136 Gbps, making it difficult to achieve 200 Gbps data transmission.
Innovation Solution
A buffer chain circuit using in-phase and quadrature inverter pairs with phase delay circuits and a phase detector comprising cells with PMOS and NMOS transistors tied to ground, allowing the VCO to operate at 40-50 GHz and support 200 Gbps data rates with a 20% frequency tuning range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a VCO operates at frequencies above 34 GHz in conventional PLL designs, then the data rate can be increased beyond 136 Gbps, but noise, parasitic capacitance and narrow tuning range make it difficult to operate at these higher frequencies
Solution Approach 1:
The buffer chain is divided into multiple stages, with each stage containing pairs of in-phase and quadrature inverters. This segmentation allows the signal to be processed in manageable steps, reducing the impact of parasitic capacitance at each stage while achieving the cumulative frequency multiplication needed for operation above 34 GHz.
Solution Approach 2:
Different circuit configurations are used for in-phase and quadrature signal paths. The in-phase side uses pairs of inverters with specific phase delay circuits, while the quadrature side uses different configurations. This local differentiation optimizes each path for its specific function, reducing noise and parasitic effects while maintaining reliable operation at high frequencies.
2Speed
If conventional PLL circuitry is used to achieve high frequency operation, then the tuning range becomes narrow, limiting the frequency adjustment capability
Solution Approach 1:
The phase delay circuits incorporate variable elements that allow dynamic adjustment of delay characteristics. This enables the PLL to adapt its tuning range dynamically, maintaining a 20% frequency tuning range across the operating band by adjusting circuit parameters in response to frequency changes, rather than being fixed at a narrow range.
3Speed
If high frequency operation is achieved through conventional means, then energy consumption increases, but the patent aims to save energy while operating at 40-50 GHz
Solution Approach 1:
The patent replaces conventional high-power amplifier stages with a buffer chain using inverter pairs and phase delay circuits. This substitution of the signal conditioning mechanism reduces power consumption by using complementary MOS logic structures that operate more efficiently at high frequencies, enabling 40-50 GHz operation with lower energy consumption than traditional approaches.
Data Source
AI summary
A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.