Quadrature Clock Correction with Duty Cycle Control
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Solution Overview
Problem
As system clock speeds increase, signal reliability and accuracy issues arise due to deteriorating phase accuracy and increased routing areas in semiconductor systems using multiple phase clocks.
Innovation Solution
A semiconductor system with a duty cycle corrector and quadrature error corrector that generates multiple phase clock signals with reduced area and improved accuracy by using analog or digital circuits, reducing the need for phase interpolators and incorporating feedback paths to minimize signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If multiple phase clock signals are used to facilitate stable operations, then system stability is improved, but routing area increases and phase accuracy deteriorates
Solution Approach 1:
The patent divides the clock signal generation into multiple independent phase signals (first, second, third, and fourth phase clock signals) that are generated separately and then combined. This segmentation allows each phase to be routed independently with optimized paths, reducing overall routing area while maintaining system stability through diverse phase availability.
Solution Approach 2:
The patent merges multiple phase clock signals at key integration points in the system. By combining first and second phase signals to generate third phase, and merging third and fourth phase signals to generate second phase, the system reduces the number of independent signal sources needed, thereby reducing routing area while maintaining stable operations.
2Stability of the object's composition
If multiple phase clock signals are used to facilitate stable operations, then system stability is improved, but phase accuracy deteriorates
Solution Approach 1:
The patent implements feedback paths where output clock signals are fed back to adjust the generation of other phase signals. Specifically, the second output clock signal is used to adjust the generation of the fourth output clock signal, and the fourth output clock signal adjusts the generation of the second output clock signal. This feedback mechanism maintains precise phase relationships and accuracy while enabling stable multi-phase operations.
Solution Approach 2:
The patent dynamically adjusts generation parameters of clock signals based on detected phase relationships. By changing the generation timing and phase offsets of different clock signals adaptively, the system maintains high phase accuracy across all four phases while ensuring stable system operation under varying conditions.
3Measurement precision
If duty cycle adjustment is applied to clock signals, then signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent employs a duty cycle corrector that serves multiple functions: it adjusts the duty cycle of input clock signals, generates precise phase relationships, and provides calibrated reference signals for other circuit stages. This multi-functionality improves signal accuracy across the system while avoiding the need for separate correction circuits for each phase, thereby limiting the increase in overall device complexity.
Data Source
AI summary
A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).