Quadrature Clock Generation With Duty-Cycle Edge Centering
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Solution Overview
Problem
Existing clock generation systems struggle to maintain proper edge alignment and symmetry of delayed clocks relative to reference clocks, especially when the duty cycle of the reference clock varies, which affects power consumption and timing accuracy in high-speed circuits.
Innovation Solution
A feedback loop mechanism adjusts the edges of the delayed clock by integrating an inductive current or capacitor charging to center the edges within the high or low states of the reference clock, using a combination of PFETs and NFETs to manage ripple voltage and ensure edge alignment across varying duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a delayed clock is generated from a reference clock with arbitrary duty cycle, then the clock can be used in high-speed circuits, but the edges of the delayed clock cannot be properly centered with respect to the reference clock phases
Solution Approach 1:
The patent employs a feedback mechanism where the delayed clock edges are monitored and adjusted based on their alignment with the reference clock phases. The system detects timing errors and applies corrections to center the delayed edges within the reference clock high and low phases, resolving the contradiction between high-speed operation and precise edge timing.
Solution Approach 2:
The patent dynamically adjusts the delay parameter of the delayed clock based on the measured alignment error. By changing the delay parameter in response to duty cycle variations and timing misalignment, the system maintains proper edge centering while operating at high frequencies, thus resolving the contradiction between speed and timing precision.
2Adaptability or versatility
If the duty cycle of the reference clock varies, then the circuit can operate under different conditions, but the timing of the delayed clock edges becomes sensitive to duty cycle changes
Solution Approach 1:
The system continuously monitors the alignment between delayed clock edges and reference clock phases, and applies real-time corrections to compensate for duty cycle variations. This feedback mechanism ensures that timing stability is maintained across a wide range of duty cycles, resolving the contradiction between adaptability and reliability.
Solution Approach 2:
The patent implements dynamic adjustment of the delayed clock parameters in response to changing duty cycle conditions. The system adapts its timing characteristics in real-time to maintain proper edge centering regardless of duty cycle variations, thus achieving both versatility and timing stability.
3Productivity
If both rising and falling edges of the delayed clock are used to trigger events, then the circuit achieves double data rate functionality, but symmetry between high time and low time is compromised by non-ideal input duty cycle
Solution Approach 1:
The patent uses feedback to independently adjust the timing of rising and falling edges of the delayed clock, ensuring that both edges are properly centered within their respective reference clock phases. This enables double data rate operation with maintained symmetry between high and low times, resolving the contradiction between productivity and stability.
Solution Approach 2:
The system applies different timing corrections to the rising and falling edges of the delayed clock based on their specific alignment requirements. By treating each edge separately and applying localized adjustments, the patent achieves proper centering for both edges while maintaining overall time symmetry, enabling reliable double data rate functionality.
Data Source
AI summary
A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.