Quadrature Clock Generator Without Polyphase Filter Loss

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Solution Overview

Problem

Existing methods for generating a quadrature clock from a two-phase clock using polyphase filters result in amplitude loss and degradation of the signal-to-noise ratio due to filtering processes.

Innovation Solution

A circuit comprising an inverting amplifier, an inverting integrator, and a buffer is used to generate a quadrature clock without filters, utilizing capacitors and resistors for coupling and inversion to produce interim signals that are then converted into a four-phase clock with maintained signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polyphase filters are used to generate quadrature clock from two-phase clock, then quadrature clock can be generated, but signal amplitude is reduced and signal-to-noise ratio is degraded

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidsignal amplitude
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent removes the filter components (capacitors and resistors forming high-pass and low-pass filters) from the quadrature clock generation circuit. By extracting these filtering elements, the circuit avoids signal amplitude reduction and maintains higher signal-to-noise ratio while still achieving quadrature clock generation through alternative means.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using filters to generate quadrature phases (which attenuate the signal), the patent inverts the approach by using filterless circuit topology with inverting amplifiers and integrators to achieve the same quadrature function without signal loss. This inverted methodology eliminates the harmful filtering effect while preserving the desired phase generation capability.

Inventive Principle:
Principle #13The other way round (Inversion)

2Productivity

If polyphase filters are used to generate quadrature clock, then four-phase clock can be produced, but signal quality is degraded due to filtering loss

Engineering Contradiction:
Improvequadrature clock generationVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent extracts and removes the filter components from the circuit architecture. By eliminating the high-pass and low-pass filter stages, the system maintains signal quality and reduces distortion while still achieving quadruple phase generation through the filterless topology using inverting amplifiers and integrators.

Inventive Principle:
Principle #2Taking out (Extraction)

3Stability of the object's composition

If filters are used in quadrature clock generation circuit, then phase spacing can be achieved, but signal amplitude is attenuated

Engineering Contradiction:
Improvephase spacingVSAvoidsignal amplitude
Core Design Contradiction:
Stability of the object's compositionVSLoss of energy

Solution Approach 1:

The patent removes filter components from the circuit, extracting the harmful amplitude-attenuating elements while preserving the phase spacing function through alternative circuit mechanisms involving inverting amplifiers and integrators that do not require filtering.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the circuit parameters and topology by replacing filter-based phase generation with an alternative approach using inverting amplifiers and integrators. This parameter change allows phase spacing to be achieved without the signal amplitude attenuation that characterizes filter-based solutions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10469061B1Quadrature clock generator and method thereof
Publication Date: 2019.11.05 REALTEK SEMICON CORP
  • US10469061B1 patent drawing
  • US10469061B1 patent drawing
  • US10469061B1 patent drawing

AI summary

A method including operations of receiving an input clock at an input node, coupling the input node to a first internal node using a first capacitor, inverting a first internal signal at the first internal node into a first interim signal at a first interim node using a first inverter, coupling the first interim node to the first internal node using a first resistor, coupling the input node to a second internal node using a second resistor, inverting a second internal signal at the second internal node into a second interim signal at a second interim node using a second inverter, coupling the second interim node to the second internal node using a second capacitor, and using a buffer to receive the first interim signal and the second interim signal and output a first phase and a second phase of an output clock.