Quadrature Clock Generation With Frequency Doubling for Low Jitter
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Solution Overview
Problem
Current semiconductor technologies face challenges in generating spectrally pure high-frequency clocks for optical transceivers due to complex circuitry, poor performance, and high power consumption, particularly in achieving high-frequency clock multiplication with low jitter and balanced differential outputs.
Innovation Solution
A high-frequency clock generation circuit that includes a phase frequency detector, a controlled oscillator, a quadrature clock generation circuit, and a frequency doubler, utilizing an injection locked quadrature ring oscillator and active feedback loops to generate fully differential and balanced clocks at higher frequencies, reducing jitter and supporting multiple baud-rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct generation techniques are used for high frequency clock multiplication, then clock frequency is improved, but spectral purity deteriorates
Solution Approach 1:
The clock multiplication process is divided into multiple stages: a first frequency doubler multiplies the reference clock by 2, followed by a second frequency doubler that multiplies the intermediate clock by 2 again to achieve 4x multiplication. This segmented approach allows each stage to operate at lower frequencies with better spectral purity while achieving the overall high frequency multiplication goal.
2Speed
If complex clock generation circuitry is used, then clock frequency is improved, but device complexity increases
Solution Approach 1:
The patent combines the reference clock and the quadrature clock signals through a merging circuit that generates both in-phase and quadrature clock outputs. This merging approach simplifies the overall circuit architecture by integrating multiple clock generation functions into a unified structure, reducing the number of separate components needed.
Solution Approach 2:
The clock generation circuit is designed to provide multiple outputs (in-phase and quadrature clocks) from a single generation core, enabling it to serve multiple functions. The same circuit architecture supports different multiplication factors and can generate clocks for various baud rates, reducing the need for separate dedicated circuits for each function.
3Productivity
If high frequency clock generation is implemented, then data rate is improved, but power consumption increases
Solution Approach 1:
The circuit incorporates dynamically controllable elements including variable gain amplifiers and adjustable frequency multipliers that can adapt their operation based on the required output frequency. This dynamic operation allows the circuit to optimize power consumption by adjusting the multiplication factor and gain levels according to the actual data rate requirement, rather than operating at maximum capacity continuously.
Data Source
AI summary
Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.