Quadrature Clock Generator Circuit for Stable 90° Phase at High Speed

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Solution Overview

Problem

Conventional clock generators struggle to maintain the correct phase relationship between in-phase and quadrature clock signals at high operational speeds and across varying operational conditions, limiting their applicability in modern electronic systems.

Innovation Solution

The development of clock generator embodiments using edge-triggered D flip-flops and tri-state inverters, which generate half-rate in-phase and quadrature clock signals with a 90-degree phase lag, ensuring reliable operation at speeds exceeding 2 GHz by optimizing critical paths and reducing the number of tri-state inverters, thereby maintaining the correct phase relationship.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional clock generator structures are used, then the circuit is simpler, but the operational speed is limited and cannot exceed 2 GHz

Engineering Contradiction:
Improveoperational speedVSAvoidcircuit structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The clock generator is segmented into multiple functional blocks including a phase selector, a quadrature generator, and buffer stages. Each block performs a specific function, allowing the overall system to achieve high speeds through modular optimization rather than monolithic design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The phase selector determines the desired phase relationship between I and Q clocks before the quadrature generation process begins. This preliminary phase selection allows subsequent stages to operate at full speed without waiting for phase alignment, enabling operation above 2 GHz.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If conventional clock generator structures are used, then the circuit structure is simpler, but the phase relationship between I and Q clocks cannot be maintained under varying operational conditions

Engineering Contradiction:
Improvephase relationshipVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The quadrature generator uses feedback mechanisms where the Q clock is derived from the I clock through a controlled delay path, and vice versa. This mutual feedback ensures that phase relationships are maintained automatically under varying operational conditions such as temperature and voltage changes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit dynamically adjusts delay parameters in the quadrature generation path to compensate for variations in operational conditions. By changing delay parameters rather than fixed timing, the system maintains correct phase relationships across different temperatures, voltages, and frequencies.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If more tri-state inverters are used in conventional designs, then the circuit can handle more conditions, but the number of elements increases and reliability decreases

Engineering Contradiction:
Improveoperational conditionsVSAvoidsignal integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The quadrature generator circuit is designed to perform multiple functions: it generates quadrature clocks, maintains phase relationships, and adapts to different operational conditions all within a single integrated structure. This multi-functionality eliminates the need for separate tri-state inverters for each condition, reducing total element count while improving reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7576584B2Clock generators for generation of in-phase and quadrature clock signals
Publication Date: 2009.08.18 ANALOG DEVICES INC
  • US7576584B2 patent drawing
  • US7576584B2 patent drawing
  • US7576584B2 patent drawing

AI summary

Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.