Quadrature Clock Interface With RC-CR Phase Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional quadrature clock generation circuits face limitations such as requiring input clock signals at least twice the frequency of generated quadrature clock signals, high power consumption, narrow operating frequency range, large area, and degradation of external clock signal quality, along with limited tunability and insufficient phase noise performance.
Innovation Solution
The proposed solution involves an oscillator interface circuit with a parallel RC-CR filter stage, where a first controllable resistor and capacitor are connected in series between pins receiving differential input clock signals, allowing for tunable and programmable resistor and capacitor values to generate quadrature clock signals with improved phase accuracy and flexibility, while preserving jitter/phase noise performance and accommodating high input frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional quadrature clock generation circuits are used, then quadrature clock signals can be generated, but the input clock signal frequency must be at least twice the frequency of generated quadrature clock signals
Solution Approach 1:
The patent employs controllable resistors and capacitors that can be programmed to different values, enabling the circuit to adapt to different input frequencies and generate quadrature clock signals with flexible frequency ratios. This eliminates the conventional constraint requiring input frequency to be at least twice the output frequency.
2Power
If conventional quadrature clock generation circuits are used, then quadrature clock signals can be generated, but power consumption is high
Solution Approach 1:
The circuit uses controllable resistors and capacitors whose values can be dynamically adjusted based on operating conditions. This dynamic adaptability allows the circuit to optimize power consumption while maintaining clock generation performance across different frequency ranges and load conditions.
3Adaptability or versatility
If conventional quadrature clock generation circuits are used, then quadrature clock signals can be generated, but the operating frequency range is narrow
Solution Approach 1:
The patent creates a universal quadrature clock generation circuit that can operate across a wide frequency range by using programmable controllable resistors and capacitors. This single circuit design replaces multiple dedicated circuits for different frequency ranges, achieving multi-functionality without proportionally increasing complexity.
4Area of stationary object
If conventional quadrature clock generation circuits are used, then quadrature clock signals can be generated, but the area occupied is large
Solution Approach 1:
The circuit employs controllable resistors and capacitors that can be reconfigured through programming rather than requiring multiple fixed-value components. This dynamic reconfiguration capability provides high tunability while occupying less area compared to conventional circuits that use multiple discrete components for different frequency ranges.
5Reliability
If conventional quadrature clock generation circuits are used, then quadrature clock signals can be generated, but the external clock signal quality is degraded
Solution Approach 1:
The patent introduces an oscillator interface circuit with controllable resistors and capacitors that acts as an intermediary between the external oscillator and the quadrature clock generation circuit. This interface circuit preserves the quality of external clock signals by providing adjustable buffering and conditioning without requiring complex signal processing paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient quadrature clock generation with low power consumption, a wide frequency range, and high performance, maintaining clock quality without degrading the external clock source, and is robust against input imbalances and layout non-idealities through calibration.
Implementation Method 1
an oscillator interface circuit with a parallel RC-CR filter stage, where a first controllable resistor and capacitor are connected in series between pins receiving differential input clock signals
Data Source
Figure 1
Figure 2~3
Figure 4A
AI summary
Apparatus and methods for oscillator interface circuits with quadrature clock generation and phase correction are disclosed. In certain embodiments, a clock system includes an external oscillator that provides a differential input clock signal, and a semiconductor die that includes a first pin that receives a non-inverted component of the differential input clock signal and a second pin that receives an inverted component of the differential input clock signal. The semiconductor die further includes an oscillator interface circuit that includes a first controllable resistor and a first controllable capacitor connected in series between the first pin and the second pin, and a second controllable resistor and a second controllable capacitor connected in series between the second pin and the first pin.