Interpolated Quadrature Clock Circuit for Low-Jitter Phase Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing quadrature clock generation techniques face issues with high power consumption, phase noise, and complexity, particularly in frequency-divider and VCO methods, and phase inaccuracies due to PVT variations in PPF-based systems, which are impractical and inefficient for low-jitter applications.
Innovation Solution
A low-cost, low-complexity quadrature clock generation system that uses an interpolation circuit to combine delayed and complementary signals, eliminating the need for power-hungry delay-locked loops and external correction loops, and optimizing phase shifts to minimize phase errors and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If frequency-divider-based quadrature clock generation is used, then quadrature clock signals can be generated, but power consumption increases and frequency doubling becomes impractical
Solution Approach 1:
Instead of doubling the input frequency and then dividing (conventional approach), the patent inverts the approach by using a single-frequency VCO and generating quadrature signals through phase shifting and combining techniques, eliminating the need for frequency doubling while reducing power consumption
Solution Approach 2:
The patent combines multiple signal processing functions (phase shifting, signal combining, quadrature generation) into a single integrated circuit block, merging the functionality of what would traditionally require separate frequency doublers and dividers, thereby reducing overall power consumption
2Power
If Quadrature VCO methods are used, then quadrature clock signals can be generated, but power consumption doubles and phase noise performance degrades
Solution Approach 1:
Instead of using two separate VCOs that consume double the power, the patent uses a single VCO and creates quadrature signals by copying and phase-shifting its output, achieving the same functional result with half the power consumption and better phase noise performance
Solution Approach 2:
The patent introduces phase shifters and signal combining circuits as intermediary elements between a single VCO and the final quadrature output, mediating the signal transformation process to achieve quadrature generation without requiring multiple high-power VCOs
3Use of energy by stationary object
If PPF-based quadrature clock generation is used, then no additional power is consumed, but phase inaccuracies occur due to PVT variations requiring filtering that adds noise and complexity
Solution Approach 1:
The patent incorporates feedback mechanisms through calibration circuits that detect and correct phase errors caused by PVT variations, maintaining high phase accuracy without requiring aggressive filtering that would add noise and complexity
Solution Approach 2:
The patent makes the quadrature generation system dynamic by implementing adjustable phase shifters and calibration mechanisms that adapt to PVT variations in real-time, maintaining accuracy without the need for fixed, complex filtering structures
4Reliability
If existing quadrature clock generation methods are used, then clock signals can be generated, but jitter and phase errors increase requiring complex correction loops
Solution Approach 1:
The patent implements self-service through on-chip calibration circuits that automatically detect and correct their own phase and jitter errors without requiring external correction loops, reducing system complexity while maintaining low jitter performance
Solution Approach 2:
The patent replaces complex external mechanical correction loops with integrated digital calibration and control circuits, substituting mechanical/external correction mechanisms with streamlined on-chip electronic solutions that achieve the same jitter reduction with less complexity
Data Source
AI summary
Presented are systems and methods for generating quadrature clock signals for high-speed signal processing and similar applications. In various embodiments, a first input signal is rotated by a first phase angle to obtain a first rotated signal that represents a first quadrature clock signal. A second input signal that is 180 degrees out-of-phase with the first signal is rotated by a second phase angle such as to produce a second rotated signal. The unaltered first input signal and the phase-shifted second signal are then combined to derive an interpolated signal. This interpolated signal may be used to generate a second quadrature clock signal. As a result, the presented systems and methods effectively addresses the challenges of low-jitter, high-accuracy clock signal generation in applications such as SERDES and other systems that require precise timing signals, thereby ensuring enhanced system performance, while reducing complexity and power consumption.